This Open Research Institute meeting provides a status update on the Opulent Voice modem development, focusing heavily on addressing technical debt and analyzing hardware constraints for space applications, particularly the AMSAT UK Mode Dynamic Transponder (MDT) project.
Key progress includes successful debugging of FIFO pointer logic, resulting in stable, clocked frame transmission, and the implementation of a scrambler producing an ideal, spectrally efficient signal. Debugging visualizations, however, reveal a high rate of false synchronization alarms triggered by noise, necessitating refinement of frame lock mechanisms.
Analysis confirms that the core modem consumes approximately 5,200 Lookup Tables (LUTs) on the Xilinx Zynq 7010, suggesting feasibility for the constrained Lattice ICE40 (5k LUTs) targeted by AMSAT UK, provided complex DSP functions (FEC, interleaving) are carefully load-balanced between the FPGA and the highly available ARM processor. The primary constraint on the FPGA choice is non-technical: the need for a QFN package for flight hardware inspection (0:43:35). The resilience of Opulent Voice for space is validated by successful data transmission during recent high-spin sounding rocket flights.
Open Research Institute Meetup (November 18, 2025) Summary
0:01:30 FIFO Debugging Visualization: Debugging utilized registers to read FIFO pointers (Tx/Rx read/write). Early testing showed initialization problems (Tx pointers misaligned) and data flow stopping when the write pointer wrapped (0:03:10).
0:04:23 Stable Data Flow Achieved: Current visualizations show "pretty darn good" performance (0:04:23), with data being metered out efficiently (0:05:33). Receive frames clock along correctly every 40ms during transmission (0:06:40).
0:07:05 High False Alarm Rate (Key Takeaway): The receiver frequently detects synchronization words, leading to spurious "frames" (green lines) when only noise is present (0:07:17). This indicates the synchronization lock mechanism is insufficient and needs to implement a hysteresis curve or rely on physical layer signal detection to suppress garbage (1:12:00, 1:17:11).
0:08:32 Spectrum Whitening: The successful implementation of the scrambler generates a desirable, fully-occupied, "white" RF spectrum, confirming efficient use of bandwidth (0:09:01).
0:17:35 Software Refactoring: Paul is addressing technical debt by modularizing the large monolithic C file and moving to a Makefile approach, including embedding the Git commit hash into the binary for reliable version tracking (0:19:12).
0:19:46 Load Balancing Decision: The next development phase involves moving DSP functions (randomization, FEC, interleaving) from the Dialogus software layer to the HDL hardware (FPGA), with the capacity to make this selection runtime switchable (0:20:32).
0:23:46 FPGA Utilization: Analysis of the Xilinx Zynq 7010 implementation shows the core modem (msk_top) uses roughly 5,200 LUTs (0:25:11). Approximately 2,300 of those LUTs are consumed by configuration/status registers used primarily for development (0:25:34), suggesting significant resources could be recovered through optimization.
0:26:30 AMSAT UK MDT Feasibility: As far as I can tell, the modem's current LUT count puts it in the feasibility ballpark for the constrained Lattice ICE40 (5k LUTs) targeted by the AMSAT UK Mode Dynamic Transponder (MDT) project (0:27:02).
0:34:40 Processor Headroom: Benchmarking shows the ARM general-purpose processor is largely underutilized, consuming only a "few percent of the CPU" (0:34:46). This supports the strategy of offloading high-rate tasks to the FPGA to reserve the processor for real-world interaction and high-level decision making (0:42:29).
0:43:35 Hardware Constraint: The 5K LUT ICE40 is specified not for performance, but because it uses a QFN package, which permits inspection of solder joints—a necessity for flight hardware—unlike the higher-capacity BGA packages (0:43:46).
0:48:43 Multi-Channel Support: The project should prioritize multi-channel support (e.g., bit slicing) to avoid the access difficulties experienced by missions like Green Cube (0:49:19).
0:51:30 Interconnect Problem (Roadblock): Data transfer between the processor and FPGA is a serious, complex issue ("eternal barrier," 0:53:10) due to limited I/O pins (I2S, SPI) on the small QFN-packaged FPGA. This fundamental limitation may force a costly switch to a higher pin count, BGA package (0:51:16).
1:01:15 Opulent Voice Space Validation: Oscar (U. Puerto Rico) confirms Opulent Voice was successfully used during a recent sounding rocket flight (1:03:00). The protocol provided reliable data downlink even when the rocket was violently spinning at about five Hertz and experiencing severe G-forces and Doppler effects (1:09:40).
1:14:15 DSES Project Update: Rick reports the Deep Space Exploration Society (DSES) is continuing the drift scan experiment (1.42 GHz hydrogen line) (1:15:39), optimizing between dual receivers (Aerospy Duo and B210) (1:16:12). Steering the 60-foot dish requires two people on site for safety, but a smaller 30-foot dish planned for the future will likely allow remote control (1:21:42).
1:25:47 FOSDEM Speaker Needed: A speaker is requested for an in-person presentation on Opulent Voice at the FOSDEM open-source conference in Brussels (Jan 31/Feb 1) (1:26:06).