This is a long and detailed walkthrough of an obsolete process node. As far as I can tell, the information is broadly correct, though likely simplified. Here is the summary.
Abstract:
This video provides an exhaustive, step-by-step breakdown of the 45nm semiconductor manufacturing process, a leading-edge node from 2007. The walkthrough covers the entire fabrication flow, starting with substrate validation and cleaning, followed by transistor isolation using Shallow Trench Isolation (STI). It then details well formation via ion implantation and the pivotal introduction of high-K metal gate (HKMG) technology, which used Hafnium Oxide and a "gate-last" flow with a sacrificial polysilicon gate to overcome leakage issues. The process continues with the creation of source/drain extensions, halo implants, and complex strain engineering techniques—tensile strain for NMOS and compressive strain using embedded Silicon-Germanium (SiGe) for PMOS. Finally, the video explains the formation of low-resistance contacts using self-aligned silicide (salicide), the replacement of the dummy gate with the final metal gate stack, and the creation of copper interconnects via the dual Damascene electroplating process.
The 45nm Semiconductor Manufacturing Process: A Step-by-Step Guide
0:28 Substrate Validation and Preparation: Before fabrication, the raw silicon wafer undergoes three critical checks: measuring electrical resistance to verify dopant concentration, using X-ray diffraction to confirm crystal lattice integrity, and using a profilometer to ensure surface flatness for lithography. The process concludes with an RCA clean to remove organic and metallic contaminants.
8:20 Transistor Isolation (Shallow Trench Isolation - STI): To prevent electrical leakage between transistors, nanoscale trenches are etched into the silicon, lined with a thin oxide layer, filled with silicon dioxide using Chemical Vapor Deposition (CVD), and then polished flat using Chemical Mechanical Polishing (CMP).
18:05 Well Formation (Ion Implantation): Using lithography to mask specific areas, dopants are fired into the silicon substrate to create P-type wells (using boron) for NMOS transistors and N-type wells (using phosphorus) for PMOS transistors.
24:28 Gate Formation (High-K Metal Gate, Gate-Last): The 45nm node's key innovation was replacing the traditional silicon dioxide gate with a Hafnium Oxide (high-K) gate to reduce current leakage. This is achieved via a "gate-last" flow, where a sacrificial "dummy" polysilicon gate is built first to endure high-temperature steps later in the process.
32:19 Halo and Extension Implants: To combat short-channel effects, "halo" pockets of dopants are implanted at an angle under the gate edges. Lightly-doped "extensions" are also created near the source and drain to protect the gate oxide from high-energy "hot" electrons.
36:02 Strain Engineering for Performance Boost: To increase transistor speed, the silicon lattice is physically strained.
NMOS: A tensile (stretching) strain is applied by depositing a silicon nitride capping layer.
PMOS: A compressive (squeezing) strain is created by etching trenches in the source and drain and filling them with a silicon-germanium (SiGe) alloy, which has a wider lattice structure.
42:11 Contact Formation (Salicide): To reduce electrical resistance at the transistor contacts, a self-aligned silicide (salicide) process is used. A thin layer of metal (like titanium or nickel) is deposited, heated to react with the exposed silicon of the source and drain to form a low-resistance metal-silicide alloy, and the unreacted metal is then etched away.
47:39 Real Gate Replacement: The sacrificial polysilicon gate is etched away and replaced with the final metal gate stack. This involves depositing specific "work function metals" to fine-tune the transistor's threshold voltage, followed by the main gate metal (e.g., aluminum).
50:40 Contact Plugs: To connect the transistors to the metal interconnect layers above, holes are etched down to the contacts and filled with tungsten.
52:41 Copper Interconnects (Damascene Process): Instead of etching metal, the Damascene process etches trenches into a dielectric layer, lines them with a barrier material, and then fills them with copper using an electroplating process known as "superfill." Excess copper is then polished away with CMP, leaving the finished wires.