This is a project update meeting for the Open Research Institute's Opulent Voice project. The central topic is the decision to abandon the Pluto SDR platform due to insufficient FPGA resources. The current design, which includes necessary forward error correction (FEC) and interleaving, exceeds the capacity of the Zynq 7010 chip, causing synthesis tools to incorrectly remove critical receiver logic and render the system non-functional. Consequently, the project is migrating to the Libre SDR, which features a larger Zynq 7020 FPGA, providing a threefold increase in logic resources. The meeting also covers technical deep dives into firmware build systems (Tzuka), SDR networking configuration issues, suboptimal sample rate handling in the receiver, and the software-to-FPGA interface for transmission. Project management updates include a planned presentation at FOSDEM and the migration of issue tracking from Trello to GitHub.
Opulent Voice Project Meeting: Migrating from Pluto to Libre SDR
1:12 - Improved Firmware Tools: A participant, Everest, is working to integrate Opulent Voice into "Tzuka," a more advanced firmware build system that simplifies testing and supports multiple SDR hardware clones. This appears to be a superior alternative to the project's current, aging Pluto MSK-based repository.
7:00 - Networking Configuration: A significant portion of the meeting is spent debugging the SDR's networking setup. The mechanism for changing the IP address via config.txt is complex, relying on boot scripts that write to flash memory, and is easily corrupted. The recommended, more robust method is to SSH into the device and use fw_setenv directly.
19:17 - Justification for "Abandoning Ship": The primary reason for switching hardware is explained. After fixing a bug in the transmitter's interleaver, the FPGA design grew too large for the Pluto's Zynq 7010. The synthesis tool, Vivado, began optimizing away parts of the receiver to make the design fit, breaking it completely. This resource limit also prevents the implementation of planned upgrades like soft-decision decoding, which would yield a 2dB performance gain.
27:42 - The Path Forward: Libre SDR: The team is moving to the Libre SDR, which uses a Zynq 7020 chip. This provides three times the logic resources (from ~18k to 53k LUTs), which is more than enough for the current design and future enhancements.
36:39 - Ongoing DSP Development: Matthew is modeling new components, like Costas loop lock indicators that also provide an SNR estimate, in Python before implementing them in HDL. This is a sound engineering practice that allows for easier validation.
43:25 - Suboptimal Sample Rate Handling: A technical discussion reveals the receiver currently uses a "poor man's decimator" by simply discarding most incoming samples from the ADC's high 66 MS/s rate. This is inefficient and risks aliasing. The correct approach, using the AD9361's built-in hardware decimation, would lower the noise floor and will be added to the issue tracker.
51:47 - Process Improvement: For better public visibility and accessibility, the project will move its issue tracking from a private Trello board to the public GitHub repository.
53:37 - Software/FPGA Interface: The team discusses the precise timing required for the host software (Dialogus) to control the FPGA's transmitter. The key challenge is managing network jitter in incoming data packets by using the transmit FIFO as an elastic buffer, ensuring data is available precisely when the hardware-generated preamble ends.