This transcript details a tour of Kioxia's Yokkaichi flash memory manufacturing facility. I don't care much for sponsored content, but the technical details of semiconductor fabrication are, as far as I can tell, inherently interesting due to the extreme engineering involved.
Target Audience/Reviewers: Semiconductor Process Engineers, Materials Scientists specializing in thin films, Data Storage Architects, and Manufacturing Automation Specialists.
Abstract:
This video showcases an exclusive tour of Kioxia's Yokkaichi semiconductor fabrication plant, focusing on the production of high-density 3D NAND flash memory, exemplified by their LC9 SSDs capable of holding 245TB per drive. The tour moves from raw silicon boule creation to the complex multi-layer deposition and wafer bonding processes. Key technological highlights include the use of Plasma-Enhanced Chemical Vapor Deposition (PECVD) for creating 218 storage layers, the innovative CMOS Directly Bonded to Array (CBA) technique which involves separately fabricating CMOS and NAND layers on different wafers before bonding and grinding the stack, and aggressive backside thinning. The facility’s massive scale (nearly 700,000 m² across seven fabs) is contrasted with its extreme cleanliness standards (Class 100-like environment). Furthermore, the discussion touches upon Kioxia's advanced defect minimization strategies utilizing AI analysis of SEM data, significant sustainability efforts including water reclamation (achieving $>90%$ recovery in new systems), and remarkable seismic isolation technology that suspends the building structure on nearly 400 specialized footings. The final stages cover die separation, wire bonding with gold filaments thinner than human hair, packaging (including solder ball deposition), and final SSD assembly, all performed with high automation, even on this prototyping line.
Summary:
0:00 Introduction & Density: Linus highlights the density achievement: four Kioxia LC9 SSDs (245TB each) approach a petabyte, thanks to 32 stacked dies per NAND package wired with gold.
1:36 Silicon Ingot to Wafer: The process starts with pulling a teardrop-shaped monocrystalline silicon ingot from molten silicon, which is then sliced into 300mm wafers.
2:09 Wafer Transport (FOUPs): Wafers travel vast distances within the facility (up to several kilometers) inside sealed carriers called FOUPs, moving between buildings via automated skyways.
3:11 Y7 Clean Room: Fab Y7 maintains extreme cleanliness to prevent particulate contamination, essential because one particle can ruin months of work.
3:35 3D NAND Construction (PECVD): Kioxia uses Plasma-Enhanced Chemical Vapor Deposition (PECVD) to build the 218 intricate storage layers required for their BiCS Flash Generation 8 memory cells.
4:26 Sub-Fab Structures: The facility uses a dense, multi-level support structure (subfab and sub-subfab) below the cleanroom to house ancillary equipment like vacuum pumps and toxic gas neutralizers, optimizing layout efficiency.
5:50 CMOS Directly Bonded to Array (CBA): Kioxia fabricates the CMOS logic on a separate wafer and then bonds it to the NAND stack using a copper layer, grinding the combined wafer thin afterward to save vertical space.
7:22 Defect Minimization via AI: AI has been used pre-trend to analyze over 35,000 data points per second from scanning electron microscopes (SEM) to identify and simulate fixes for defects, improving yield.
8:41 Facility Scale: Fab Y7 alone covers 3 million square feet, requiring cranes to lift equipment up seven stories for installation.
9:29 Sustainability (Solar & Water): The facility incorporates large solar deployments (one site over 2MW peak) and extensive water reclamation systems, achieving over 90% recovery rates in newer fabs, necessary because chip manufacturing demands ultra-pure water.
12:22 Wafer Thinning: After bonding the CMOS and NAND wafers, the top wafer is ground down from $\sim 800 \mu m$ to $30-40 \mu m$ to maintain overall package thinness.
13:44 Die Cutting and Wiring: Individual dies are cut from the thinned wafer. Stacks of up to 32 dies are interconnected using incredibly fine gold wires (quarter the thickness of human hair).
14:40 Packaging (Resin and Solder Bumps): Bonded dies are protected by pouring resin over them and baking; subsequently, solder balls (for BGA interface) are precisely placed onto the backside contacts via vacuum head and reflowed in an oven. Defective packages are identified (missing laser engraving) and discarded.
16:31 SSD Assembly: Packaged NAND dies and DRAM caches are placed onto blank PCBs using high-speed pick-and-place machines, followed by solder paste application, vision inspection, and reflow in a multi-zone oven to prevent brittle solder joints.
18:18 Earthquake Protection: The building structure is decoupled from the foundation using nearly 400 specialized seismic dampers/footings made of materials like natural rubber, allowing the building to move up to 60 cm during an earthquake.