Domain: Semiconductor Manufacturing & Process Integration
Persona: Senior Semiconductor Process Integration Engineer
2. Summarize (Strict Objectivity)
Abstract:
This technical overview details the fabrication sequence of the 45-nanometer (nm) CMOS process node, specifically the High-K Metal Gate (HKMG) "Gate Last" flow popularized in 2007. The process encompasses substrate preparation, electrical isolation via Shallow Trench Isolation (STI), well formation using ion implantation, and the transition from silicon dioxide to hafnium oxide dielectrics. Key advancements discussed include strain engineering (SiGe epitaxy and tensile capping layers) to enhance carrier mobility and the implementation of the Damascene process for copper interconnects. The summary tracks the integration of various deposition (CVD, ALD, PVD), lithography, and metrology techniques required to maintain parametric and catastrophic yield at sub-micrometer scales.
45nm Process Node: Technical Fabrication Sequence and Integration
0:00 Historical Context: The 45nm process node entered high-volume production in 2007, marking a pivotal shift in scaling and materials science.
1:06 MOSFET and CMOS Fundamentals: Logic fabrication utilizes Complementary Metal Oxide Semiconductor (CMOS) structures, pairing NMOS (electron transport) and PMOS (hole transport) transistors. Device scaling necessitates shrinking contacts and interconnects while maintaining parametric yield (performance specs) and catastrophic yield (functional success).
3:28 Substrate Preparation and Metrology: Wafers produced via the Czochralski method undergo rigorous checks for dopant concentration (four-point probe), crystallographic integrity (X-ray diffractometry), and surface flatness (stylus profilometry).
6:25 RCA Cleaning Protocol: The industry-standard RCA clean involves two primary stages: SC1 (alkaline bath for organic films) and SC2 (acidic bath for metal contaminants).
8:17 Shallow Trench Isolation (STI): Replacing the older LOCOS method, STI prevents current leakage between adjacent transistors. The process involves etching nanoscale trenches, lining them with thermal oxide, and filling them with silicon dioxide via Tetraethyl Orthosilicate (TEOS) Chemical Vapor Deposition (CVD).
16:10 Planarization (CMP): Chemical Mechanical Polishing (CMP) is used to flatten the landscape, utilizing a silicon nitride stopping layer to ensure precise grind depth.
18:08 Well and Tub Formation: NMOS and PMOS transistors are built on P-type and N-type wells, respectively. Doping is achieved via ion implantation of boron or phosphorus, followed by Secondary Ion Mass Spectrometry (SIMS) to verify dopant concentration.
24:31 High-K Metal Gate (HKMG) Transition: To combat short-channel effects and leakage, silicon dioxide gate insulators were replaced with hafnium oxide ($HfO_2$). Atomic Layer Deposition (ALD) is utilized to deposit $HfO_2$ at thicknesses of 1-2 nm.
26:05 Gate-Last Flow: The "Gate-Last" or "Replacement Metal Gate" flow involves building a sacrificial polysilicon dummy gate to align the source and drain, which is replaced with metal only after high-temperature annealing steps are complete.
32:19 Halo Implants and Extensions: Pocket/halo implants suppress lateral dopant spreading, while lightly doped extensions protect the gate oxide from hot carrier injection.
36:02 Strain Engineering: Mobility is enhanced via tensile strain for NMOS (silicon nitride capping) and compressive strain for PMOS (epitaxial Silicon-Germanium or "SiGe" in the source/drain regions).
42:09 Silicide/Salicide Formation: To reduce electrical resistance at contacts, metal-silicon alloys (silicides) are formed. The "salicide" (self-aligned silicide) process uses titanium, nickel, or cobalt sputtered onto the silicon and annealed to create low-resistance C54 phase layers.
46:30 Replacement Metal Gate (RMG) Construction: The dummy gate is removed via wet etch (TMAH). Work function metals (e.g., Titanium Nitride for PMOS, Titanium Aluminide for NMOS) are deposited to tune threshold voltages before the final aluminum or tungsten gate fill.
50:36 Contact Plugs: Vertical connections (plugs) are established by etching through the interlayer dielectric (ILD) and filling with tungsten over a titanium nitride glue layer.
52:41 Copper Interconnects and Damascene Process: Copper replaced aluminum for interconnects due to lower resistivity. Because copper cannot be easily dry-etched, the Damascene process is used: etching trenches into low-k dielectrics, applying a tantalum barrier and copper seed layer, and utilizing "superfill" electroplating.