Domain: Microelectronics and Integrated Circuit (IC) Design Engineering
Persona: Senior Analog Design Architect & Technical Lead
Part 2: Summary
Abstract:
This transcript serves as the introductory lecture for the 2026 "Advanced Integrated Circuits" (AIC) course at NTNU, delivered by Carsten Wulff, an IC Scientist at Nordic Semiconductor. The course focuses on bridging the gap between theoretical microelectronics and industry-standard silicon production. Wulff outlines a "Digital-on-top" design methodology, utilizing the Skywater 130nm Open Source PDK. Central to the curriculum is a hands-on project requiring students to design and verify a temperature sensor, with the specific opportunity for a physical tape-out via Tiny Tapeout. The lecture emphasizes the necessity of understanding analog fundamentals in a continuous physical world, the rigor of PVT (Process, Voltage, Temperature) corner simulation, and the transition from schematic entry to GDSII layout.
Course Overview and Technical Framework:
0:36 Instructor Background: Carsten Wulff, an IC Scientist with 18 years of experience at Nordic Semiconductor and an Associate Professor at NTNU, specializes in ADCs, DC-DC converters, and pre-production technical issues.
4:22 Pedagogical Philosophy: The course defines roles within the "Research Universe": PhDs investigate the unknown, Master’s students learn current possibilities, and Industry simplifies complex possibilities for human benefit.
7:30 Primacy of Analog Design: Despite digital abstractions, the physical world is inherently analog (voltage, time, momentum). All ICs require analog components for power supplies, biasing, and clocking.
10:15 Analog Design Flow: The iterative process involves schematic capture, SPICE simulation, and physical layout. Layout requires the generation of masks for the foundry, representing various semiconductor layers.
15:42 PVT Corners and Reliability: Designers must verify circuits against "corners"—extreme variations in process (fast/slow MOSFETs), voltage, and temperature—as well as Monte Carlo analysis to ensure high-volume manufacturability.
18:53 Design Standardization: To manage complexity in lower nanometer nodes, Wulff advocates for the use of "standard cells" (quantized transistors with fixed widths/lengths) to ensure layout consistency and reduce parasitic variation.
23:58 Full Chip Integration: Most complex SoCs utilize a "Digital-on-top" strategy, where analog IPs are instantiated within a SystemVerilog hardware description framework.
28:26 Silicon Tape-out Opportunity: Through Tiny Tapeout and Nordic Semiconductor sponsorship, students may submit their 130nm designs for fabrication at the Skywater foundry, transitioning from GDSII stream formats to physical silicon.
45:00 Verification and CAD Tools: The process requires a strict verification plan, including LVS (Layout Versus Schematic) and DRC (Design Rule Checks). Tools utilized include Xschem (schematic), Ngspice (simulation), Magic (layout), and Netgen (LVS).
56:00 Milestone 0 and Project Deliverables: The course grade is split between a final exam (55%) and a project (45%). Milestone 0 involves the installation of the open-source EDA suite and the successful design of a current mirror using the "Janeve" transistor library.
1:04:49 Industry Realities: Student testimonials highlight the course as highly rewarding but labor-intensive, requiring deep engagement with open-source EDA workflows and existential problem-solving.