This material outlines a comprehensive mixed-signal Integrated Circuit (IC) design project for the 2026 Advanced Integrated Circuits course. The technical objective is the end-to-end development of a local on-die temperature sensor using the Skywater 130nm (Sky130) process. The design addresses the critical industry challenge of managing exponential leakage current variations in System-on-Chip (SoC) architectures by providing real-time thermal data to optimize power regulator efficiency.
The proposed architecture utilizes a Bandgap Reference (BGR) core to generate Proportional-To-Absolute-Temperature (PTAT) currents and Complementary-To-Absolute-Temperature (CTAT) voltages. These analog signals drive a relaxation oscillator to convert thermal data into a frequency domain signal, which is subsequently digitized by a Verilog-defined Finite State Machine (FSM) and counter against a 32.768 kHz reference clock. The design flow utilizes an open-source EDA stack, including Xschem for schematic capture, Ngspice for multi-corner/Monte Carlo simulation, Magic for physical layout, and Netgen for Layout Versus Schematic (LVS) verification. Successful designs meeting GDSII specifications and Design Rule Checks (DRC) are eligible for silicon fabrication via the Tiny Tapeout shuttle.
Project Specification and Design Review Summary
0:01:16 Historical Precedent: Documentation of the 2025 successful tapeout (TT-Sky25a) confirms the viability of the current sensor architecture and the open-source toolchain for producing functional silicon.
0:02:14 Thermal Management Logic: Modern SoCs (e.g., Nordic nRF54L15) exhibit current consumption swings from 700nA to 100mA. Because leakage current is exponentially dependent on temperature and threshold voltage ($V_t$), localized temperature sensing is required to dynamically scale regulator bias and maintain efficiency.
0:09:51 System Architecture: The sensor is a mixed-signal chain consisting of a BGR core (current/voltage generation), a relaxation oscillator ($I \to F$ conversion), and a digital back-end (frequency measurement via cycle counting).
0:13:56 Milestone 1 (Bandgap Design): Focuses on the "Bandgap" core using a 1:8 BJT/diode ratio to generate PTAT current. Key challenges involve Operational Transconductance Amplifier (OTA) stability and ensuring proper startup conditions to avoid zero-current states.
0:14:57 Milestone 2 (Oscillator Design): Implements a relaxation oscillator where $I_{PTAT}$ charges a capacitor until it reaches the $V_{CTAT}$ trip point. This produces a temperature-dependent frequency based on the $I=C(dv/dt)$ relationship.
0:18:15 Technical Specifications: Design constraints include a silicon area $< 10,000 , \mu\text{m}^2$, active current $< 100 , \mu\text{A}$, and target accuracy of $\pm 10^\circ\text{C}$ across $0\text{--}70^\circ\text{C}$ with a single-point trim.
0:22:54 EDA Toolchain Integration: The project mandates a specific file structure for compatibility with automated GitHub Workflows, which execute GDSII generation, DRC, and LVS upon every commit to the repository.
0:43:19 Simulation Strategy: Verification requires simulating across "corners" (process, voltage, temperature) and Monte Carlo analysis to account for device-to-device mismatch and parasitic capacitance extracted from the physical layout.
0:49:50 Digital Modeling: A Verilog model of the analog oscillator is utilized for rapid FSM verification, enabling digital logic design without the high computational overhead of full SPICE transient simulations for the counter logic.
0:56:03 Calibration and Compensation: Post-simulation analysis involves using Python to calculate offset and gain errors. A second-order polynomial compensation is recommended to map raw digital counts back to precise temperature, accounting for non-linearities in the silicon bandgap and resistor temperature coefficients.
1:02:07 Industry Sponsorship: Nordic Semiconductor provides sponsorship for the physical tapeout (TTSKY26b), bridging the gap between academic design and commercial manufacturing.