Domain: Aerospace Communications and Digital Signal Processing (DSP) / FPGA Engineering.
Persona: Senior Systems Architect and Lead FPGA Engineer.
2. Expert Review Group
This material is most relevant for Digital Communications Systems Engineers, FPGA/HDL Designers, SDR (Software Defined Radio) Developers, and Open-Source Aerospace Researchers. These professionals focus on hardware-software co-design, synchronization algorithms, and porting complex waveforms to resource-constrained embedded platforms.
3. Summary (Strict Objectivity)
Abstract:
This meeting transcript details the technical status and roadmap of the Open Research Institute (ORI) projects as of early 2026. The primary focus is the implementation of the "Opulent Voice" digital radio protocol and its transition from the Pluto SDR (Zynq 7010) to the more resource-capable Libra SDR (Zynq 7020). The technical discussion covers critical FPGA debugging efforts, including resolving clock domain crossing (CDC) issues, fixing variable range declaration bugs in VHDL that caused spectral spurs, and re-enabling LVDS tuning to restore Q-channel operation. Furthermore, the team outlines progress on a 24-bit optimized sync word for frame alignment and a new $I^2 - Q^2$ lock detection metric for the receiver chain. Future milestones include integrating the DVB-S2 downlink with the Opulent Voice uplink for prototyping in late 2026, with planned demonstrations at FOSDEM and DEF CON.
Project Technical Status and Engineering Review:
02:26 Bricksat-P Development: The team is recreating an electronic propulsion-based CubeSat (Bricksat-P) based on 2014 patents. Deployment is scheduled for the June–August window of 2026.
05:23 Receiver Lock Detection Architecture: Proposal for a lock detector comparing energy levels between I and Q arms. The implementation utilizes the absolute value of $I^2 - Q^2$ against a configurable threshold to determine phase/frequency lock.
08:15 Metric Estimation and Quantization: Discussion on estimating $E_s/N_0$ using the $I^2 - Q^2$ approach. To avoid high-resource division operations on the FPGA, the team is exploring quantization of the numerator/denominator via lookup tables (LUTs) and averaging over 1024-symbol intervals.
14:18 Hardware Migration (Pluto to Libra SDR): Migration from the Zynq 7010 to the Zynq 7020 (Libra SDR) was necessitated by logic density requirements for the full framed protocol (Forward Error Correction, interleaving, and randomization).
18:25 Clock Domain Crossing (CDC) & LVDS Interface: Transitioning to LVDS mode on the Libra SDR required implementing a standalone clock divider and synchronization registers to manage data transfer between the 61.44 MHz modem clock and the higher-frequency LVDS interface clocks.
23:51 VHDL Range Declaration Bug ("The Great Spur Hunt"): A critical bug was identified where a natural range declaration error in the state machine (not caught in simulation) caused the encoder to repeat the first byte of data, creating periodic spurs in the transmit spectrum.
26:32 Q-Channel Suppression and Tuning: A 3dB image and total Q-channel failure were resolved by re-enabling the radio chip’s internal LVDS tuning process. Previous failures in tuning were attributed to an incorrect assumption that the custom FPGA logic was interfering with the SPI-based calibration.
29:05 Sync Word Optimization: The team transitioned from concatenated Barker codes (3:1 ratio) to an optimized 24-bit sequence achieving an 8:1 peak sidelobe to main lobe ratio. This improves autocorrelation properties and supports soft-decision decoding.
35:03 Resource Constraints on Lattice ICE FPGAs: Analysis of the AMSAT UK mode dynamic transponder revealed that the Opulent Voice protocol exceeds the logic capacity of the Lattice ICE FPGA. The project will pivot to developing a "Weak Signal Detector" for this specific platform.
38:53 State Machine Debugging with ILA: Current development is stalled by a decoder state machine lock-up during the FEC (Forward Error Correction) stage. The team is utilizing Integrated Logic Analyzer (ILA) cores to probe internal signals and trigger on state transitions in real-time.
46:53 Frame Sync Error Visualization: Debugging via register sampling (every 10ms) revealed impossible frame sync error counts. This visualization is being used to isolate issues between the sync detector and upstream digital processing.
51:52 2026 Integration Roadmap: Prototyping for a combined Opulent Voice uplink and DVB-S2X downlink is slated for late 2026. The system is intended to function as a digital transponder for both terrestrial repeaters and space segments.