Domain Adoption: Senior Avionics Systems Engineer specializing in Legacy Digital Interface Implementation and Embedded Systems Programming.
Abstract
This technical analysis details the interfacing and operational verification of a Distance Measuring Equipment (DME) indicator utilizing the legacy ARINC 561 6-line digital interface. The protocol implementation requires generating 32-bit data words, including the octal label 201 (81 hex) and four Binary-Coded Decimal (BCD) fields representing distance in miles, necessitating bit and BCD permutation due to LSB/MSB ordering. The generation was achieved using a Microchip Curiosity development board, leveraging the microcontroller's SPI bus configured for 32-bit transmission and an external interrupt for precise synchronization control.
Further analysis covered hardware features, including a specific fault detection circuit designed to signal a dead decimal point lamp. The indicator was also successfully integrated with a DME test set via a custom acquisition board. This necessitated writing a highly optimized assembly language routine to extract synchronized dual pulses, involving fine-tuning the microcontroller's internal clock frequency to $8.09 \text{ MHz}$ to achieve a $1.236 \mu s$ sampling loop ($0.1$ mile resolution). The effectiveness of the pulse averaging routine was confirmed using a custom 3-bit Digital-to-Analog Converter (DAC) to visualize accumulated pulse data on an oscilloscope.
Summary
0:03 DME Indicator Interface: The DME miles indicator utilizes an ARINC 561 6-line interface, comprising three pairs of lines: Digital Synchronization, Digital Clock ($11 \text{ kHz}$), and Digital Data.
0:41 ARINC 561 Protocol Structure: The data transmission consists of a 32-bit word. The first byte is the label (201 octal or 81 hex). The second byte is a "register clear" command (low level). The remaining 16 bits contain four BCD data fields used for the distance display.
1:11 BCD Data Permutation Requirement: Due to the LSB-to-MSB transmission order, all bits within the BCD data fields must be permuted prior to transmission.
1:36 Synchronization Logic: The digital synchronization line is set to a low level during the low phase of the clock signal input.
1:47 Interface Implementation Hardware: Testing was performed using a Microchip Curiosity Development Board.
2:13 Digital Bus Configuration: The ARINC 561 interface was synthesized using the microcontroller's SPI bus in a 32-bit configuration, with an external interrupt (Interrupt 0) controlling the synchronization line based on the clock count (Sync line goes low at clock 8 and high one clock cycle later).
2:53 Data Manipulation Technique: Data permutation (of the 16 data bits) was handled in C code using a union structure and a custom BCD swap lookup table to convert the 16-bit value into a string, permute the BCD bits, and feed the result into the SPI low word.
4:03 Portability Constraint: The implementation is cautioned as non-portable due to its dependence on the compiler's endianness.
4:13 Test 1 (Generator Verification): Using an ARINC 561 generator, oscilloscope traces confirmed the expected signal sequence: synchronization line dropping low at bit 8, followed by the 81 hex label and the 32 clock pulses.
5:49 Decimal Dot Fault Detection: The indicator features a specific failure detection circuit for the decimal point lamp, utilizing an NPN transistor and a shunt resistor to detect lamp current flow. Shorting the transistor grid to ground simulates a fault, causing the indicator to alternate between the figure and a minus sign.
7:25 Test 2 (DME Pulse Extraction): A DME test set was used to feed distance pulses to a separate board designed for synchronous dual pulse extraction (used for range calculation).
8:04 High-Precision Timing: The acquisition routine required a sampling interval of $1.236 \mu s$ to achieve $0.1$ mile resolution. This required adjusting the internal $8 \text{ MHz}$ clock frequency to $8.09 \text{ MHz}$ (exploiting the $\pm 1.5%$ adjustment range).
8:32 Assembly Language Optimization: The acquisition loop was implemented in assembly language to ensure execution speed consistency, achieving exactly 10 CPU cycles ($1.236 \mu s$) per loop iteration.
9:12 Pulse Averaging Algorithm: The core acquisition uses the powerful ADDWBC (addition with carry) instruction to copy the input pulse signal (via carry bit C) and accumulate counts across multiple acquisitions (set to 7) to perform averaging and differentiate synchronized pulses from noise.
10:02 Pulse Validation: The extraction function validates pulses by measuring the time between two pulses, confirming separation is either 12 or $30 \mu s$ before returning the distance value.
10:42 DAC Visualization: A simple 3-bit DAC was constructed to visualize the resulting averaged pulse table on the scope, confirming that synchronized pulses exhibit a significantly higher amplitude than random noise.