The appropriate group of people to review this topic are Academic Leaders and Industry Analysts specializing in Semiconductor Workforce Development and Open-Source Hardware Initiatives.
Abstract:
This material summarizes the outcomes and experiences associated with the first-ever Analog IC Design competition held in Sri Lanka, sponsored by CEDA, Cass, IEEE, and Skill Surf. The challenge required participants to design and execute the layout of an audio-frequency operational amplifier (op-amp). Three top designs, created by undergraduate students from the University of Moratuwa, were aggregated into a single tiny tapeout (TTO) submission for fabrication in November 2025. The interview with the winners provides critical insight into the nascent state of the Sri Lankan semiconductor sector, which is currently focused primarily on assembly rather than design or fabrication. The participants emphasized the competition's utility as a highly structured, goal-oriented project that provided essential hands-on experience with the entire analog design flow, leveraging open-source tools (OSIC, KLayout) and real Process Design Kits (PDKs). Future plans for all winners involve pursuing advanced degrees (PhDs) and careers in analog IC or embedded systems design.
Summary:
0:02 Competition Overview: The first Analog IC Design competition in Sri Lanka (organized by Cass, CEDA, IEEE, and Skill Surf) tasked participants with designing and laying out an operational amplifier capable of amplifying audio frequencies. Three top submissions were combined for a single tiny tapeout design submitted for fabrication in November 2025.
0:49 Participant Background: The three winners interviewed (Nilakna, Pravindu, and Rajendan) are all third-year undergraduates at the University of Moratuwa studying Electronics and Telecommunication Engineering. Their initial interest in electronics originated from early school exposure to components like Arduino and transistors, and low-level hardware projects found on YouTube.
4:33 Sri Lankan Semiconductor Landscape: The domestic semiconductor industry is described as immature, focusing predominantly on component and device assembly, with limited activity in design and fabrication. Undergraduate exposure to IC design is low, though a growing community of local engineers is working to establish mentorship and resources.
6:25 Competition Structure and Value: The competition was highly beneficial, functioning as a "guided project" with defined specifications and timelines, helping students master the design pipeline, including the use of open-source silicon (OSIC) tools and PDKs.
8:04 Design Flow Mastery: The process pushed participants through the complete design flow, from initial paper-based calculations and schematic simulation to post-layout verification and SPICE extraction.
11:00 Layout Challenges (Open Source): Participants noted that the IC layout process, done using KLayout, lacked the automated guidance found in traditional PCB tools (e.g., Altium), requiring extensive manual effort, detailed floor planning (initially mapped out on Excel), and careful adherence to Design Rules (DRCs).
14:09 Toolchain Constraints: A significant technical hurdle identified was the lack of P-cell support for the Sky130 PDK within KLayout, necessitating the generation and importation of P-cells from Magic software before proceeding with layout.
15:28 Model Accuracy: One winner noted surprise at how closely initial hand-calculated mathematical models and W/L ratios matched actual transistor behavior in schematic simulations, requiring less fine-tuning than anticipated. Post-layout simulations also closely tracked schematic-level results (within millivolts and hertz of bandwidth).
17:05 Future Career Trajectory: All three students expressed enthusiasm for microelectronics, intending to pursue careers in analog IC design, FPGA systems, and embedded electronics, with plans to pursue PhDs following their undergraduate degrees.