Domain: Aerospace Systems Engineering / Digital Signal Processing (DSP) / Satellite Communications
Persona: Lead Systems Architect (Space Systems & Embedded Hardware)
Phase 2: Abstract and Summary
Abstract:
This technical exchange details the development of the Mode Dynamic Transponder (MDT) for the AMSAT-UK FunCube+ satellite mission, a collaboration between the Open Research Institute (ORI) and AMSAT-UK. The primary design objective is a low-power, weak-signal digital receiver utilizing Successive Interference Cancellation (SIC) to extract signals from a 30-40 kHz passband. Due to strict power constraints (targeting approximately 0.5W), the architecture utilizes a Lattice iCE40 FPGA as a DSP co-processor for channelization, paired with an STM32 microcontroller for general-purpose processing. The discussion covers hardware selection—specifically the preference for inspectable QFN packages and open-source toolchain compatibility—and the transition from high-level Python simulations to HDL-based resource utilization analysis. A critical requirement is the ability to reconfigure the FPGA bitstream on-orbit to allow for post-launch experimentation and mode updates.
MDT Development and SIC Implementation for FunCube+
0:35 Meeting Objectives: ORI outlines the project status for the FunCube+ satellite mission, focusing on the Mode Dynamic Transponder (MDT) and weak-signal digital experiments.
1:41 Weak Signal Strategy: The project lead (Martin, M0LNG) confirms a shift toward "digging signals out of a passband" via Successive Interference Cancellation (SIC) rather than traditional service translation.
2:55 Channelization Feasibility: Simulations suggest that 3–4 channels within a 30–40 kHz bandwidth are achievable on the Lattice iCE40 FPGA.
5:23 Power Constraints and Platform Selection: The design prioritizes the iCE40 and STM32 architecture to stay within a 0.5W power budget, contrasting with higher-performance but power-hungry SoC platforms like the Xilinx Zynq 7020 (which typically draws >2W).
7:36 ADC Precision and Signal Path: Discussion on using high-precision external Analog-to-Digital Converters (ADCs) versus native STM32 converters. The proposed data path flows from the ADC to the FPGA via I2S, with channelized data reaching the MCU via SPI.
11:33 SIC Brute Force Search: The SIC implementation involves a brute-force search for high-energy peaks within a bandwidth chunk, processed sequentially to isolate individual signals.
14:18 Transition to CubeSat Form Factor: The project is moving from desktop development boards to the CubeSat PC-104 form factor, with a deadline for "bench-ready" hardware by October 2026.
17:42 Hardware Optimization: Consideration of combined audio codecs (ADC/DAC) to reduce footprint and power. High precision is prioritized for the receiver (RX) side, while the transmitter (TX) side may utilize the MCU’s internal DAC.
19:34 Component Rationale: The iCE40 was selected for its low power consumption, compatibility with open-source toolchains (e.g., Yosys), and availability in QFN packaging for visual solder joint inspection.
22:43 HDL Simulation and LUT Benchmarking: Current efforts are transitioning from Python (Jupyter) notebooks to HDL synthesis to determine the specific Look-Up Table (LUT) count and routing efficiency on the iCE40.
26:43 Bus Bottlenecks: A primary technical concern is the bandwidth and resource overhead of serial buses between the FPGA fabric and the external processor, unlike integrated SoC interconnects.
28:32 Mission Success Criteria: Critical launch requirements include a simple functional transponder and a robust on-orbit bitstream update capability to enable long-term software-defined experimentation.
Phase 3: Reviewer Identification
To evaluate this topic effectively, a panel of experts in the following fields is required:
Lead FPGA Engineer: To verify the LUT utilization and routing feasibility of SIC on the iCE40.
Satellite Power Systems (EPS) Engineer: To validate the 0.5W power budget across the SDR chain.
Amateur Satellite (AMSAT) Coordinator: To ensure the transponder modes align with the requirements of the global HAM community.
Embedded Software Architect: To review the I2S/SPI data flow and MCU-FPGA interface stability.