The January 27, 2026, Open Research Institute (ORI) Projects Meetup serves as a comprehensive technical synchronization for several open-source aerospace and digital communication initiatives. Key focus areas include the optimization of the Open Component Portability Infrastructure (OpenCPI) for DVB-S2 implementation on Zynq UltraScale+ architectures, and the finalization of the Opulent Voice protocol specification (v1.1). The meeting highlights the successful transition of Opulent Voice toward interoperability through refined Forward Error Correction (FEC) and interleaving schemes.
Engineering discussions also detail the development of a Mode Dynamic Transponder (MDT) for the AMSAT-UK FunCube Plus satellite, specifically balancing power constraints against FPGA (Lattice iCE40) and MCU (STM32) utilization. Progress on ground station capabilities is reported, including NASA-coordinated tracking for the Artemis II mission and high-frequency (8 GHz) performance validation of the Haswell deep-space dish. The session concludes with a high-fidelity VHDL simulation of a symbol lock detector, demonstrating robust acquisition within a 13ms window despite frequency offsets, providing a blueprint for upcoming hardware-in-the-loop testing.
Meeting Summary: Aerospace Systems and Digital Protocol Development
1:16 OpenCPI and DVB-S2 Progress: Successful resolution of AXI4-Lite register reset issues on the Xilinx ZCU104. Current work focuses on verifying GSC padding data flow from CPU to FPGA fabric via ILA (Integrated Logic Analyzer).
5:38 OpenCPI Framework Architecture: Discussion on the utility of OpenCPI for heterogeneous computing, allowing application deployment across diverse hardware (e.g., Zynq 7000 vs. UltraScale+) without full redesigns.
10:45 Opulent Voice Protocol v1.1: Finalization of the digital uplink specification. Key updates include adoption of CCSDS randomization standards, NASA convolutional coding for FEC, and an optimized row-column interleaver to enhance link robustness.
11:45 High-Fidelity Audio Strategy: Opulent Voice prioritizes audio quality by utilizing a 16 kbps vocoder over an 81 kHz bandwidth, intentionally sacrificing VHF compatibility for superior performance on UHF and higher frequencies.
24:23 FunCube Plus / MDT Design: Technical trade-offs for the Mode Dynamic Transponder. The system will utilize an iCE40 FPGA for polyphase channelization and a high-precision 24-bit ADC, maintaining a strict power budget of approximately 0.5W.
42:11 Hardware Packaging and Inspection: Decision to utilize QFN packaging for the iCE40 FPGA to ensure solder joint inspectability on the CubeSat form factor, avoiding the X-ray requirements of BGA packages.
53:07 Future GIO and ESA Collaboration: Prototyping schedule for a digital-based amateur transponder for Geostationary (GEO) deployment. The goal is to move beyond "bent-pipe" linear transponders toward on-board digital signal processing and quality-of-service (QoS) management by 2026.
1:04:29 NASA Artemis II Tracking Challenge: DSES (Deep Space Exploration Society) involvement in tracking the manned lunar capsule. Logistics involve 10-day continuous staffing at the Haswell site and precise antenna steering (0.5-degree beamwidth).
1:16:00 High-Frequency Dish Validation: Successful 8 GHz beacon tests confirm the Haswell dish’s surface accuracy and steering precision (0.1-degree resolution), exceeding original 1950s-era design specs for tropospheric studies.
1:22:52 Venus-Earth-Venus (EVE) Experiment: Planned October 2026 attempt to recover communications bounced off Venus. The link budget requires combining five 250W transmitters for a 1.5 kW total output to overcome the significant path loss.
1:38:17 Symbol Lock VHDL Simulation: Demonstration of a Costas loop implementation for symbol acquisition. The simulation confirms stable lock acquisition at 13ms with frequency offset, utilizing I/Q arm accumulation and squared error signal thresholding.
1:57:34 FPGA Resource Optimization: Analysis of bit-width tuning for DSP slices in the Zynq 7020. Reducing accumulation widths to 24 or 28 bits is recommended to maximize hardware efficiency without sacrificing lock detector sensitivity.