This material is most relevant to Digital Communications Systems Architects, FPGA/DSP Engineers, and Open-Source Satellite Hardware Developers. The technical depth regarding clock domain crossing, DVBS2 encapsulation, and SDR hardware clones requires a background in embedded systems and signal processing.
Senior Systems Architect Review
Abstract:
The Open Research Institute (ORI) FPGA Meetup (February 10, 2026) provides a technical status update on several open-source digital communications projects. Key developments include successful DVBS2 signal detection using the ZC104 platform, achieving voice interoperability between C++ software modems and hardware implementations on the Libre SDR, and the integration of an extensible "slash command" structure for the Interlocator interface. Technical challenges discussed include first-frame synchronization loss in the Opulent Voice protocol and hardware inconsistencies in AliExpress-sourced Libre SDR units. A significant portion of the session focuses on the use of AI-assisted coding (Claude Code) to refactor AXI bus clock domain crossing logic and to generate high-fidelity Python models for accelerated system-level simulations and Costas loop gain optimization.
Meeting Summary: Progress Report on Open-Source Digital Communications and FPGA Architectures
0:00:48 DVBS2 Milestone: Aaron reports successful detection of a DVBS2 signal using the ZC104 and Pico tuner. Upcoming work focuses on software development for IP data injection into the encoder.
0:02:25 GSSE Support and Hardware Migration: The team is reverting from the Pico tuner to the predecessor "Mini Tuner" due to superior support for Generic Stream Encapsulation (GSSE) within the British Amateur Television Group framework.
0:05:04 Opulent Voice Interoperability: Two-way voice communication achieved between a C++ software modem on a Pluto SDR and the hardware modem on a Libre SDR.
0:05:50 Interlocator UI Resilience: Developers identified a failure in the web interface to display "UI bubbles" and text messages. This is attributed to the modem failing to lock quickly enough to decode the initial PTT start message or the first frames of a transmission.
0:07:50 Physical Layer Lock Analysis: Initial testing of a new physical layer lock indicator shows acquisition times between a quarter and a half-frame. Investigations continue into why the first frame is consistently lost despite the presence of a preamble.
0:12:30 Libre SDR Hardware Quirks: Field reports on Libre SDR units (AliExpress clones) highlight inconsistent serial port configurations and unreliable booting compared to authentic Pluto SDRs. Skepticism remains regarding the functionality of the onboard 1PPS and frequency reference inputs.
0:20:19 Extensible Command Structure: Implementation of a "slash command" module for Interlocator, modeled after MMO and Discord interfaces. The first functional module is a "Dragon Dice" roller for tabletop gaming over amateur radio.
0:34:53 Future GEO and Satellite Initiatives: ORI is participating in the ESA-funded "Future GEO" initiative to develop a digital multiplexing successor to QO-100. AMSAT UK progress continues on the Mode Dynamic Transponder (MDT) using an iCE40 FPGA and STM32 co-processor.
0:40:12 AXI Bus Logic Refactoring: Matthew implemented a resynchronization widget on the AXI bus to eliminate individual clock domain crossing (CDC) logic for Configuration and Status Registers (CSRs). This moves the CSRs into the modem clock domain for simplified correlation.
0:43:07 AI-Assisted Implementation: The team successfully utilized "Claude Code" to automate the instantiation of the AXI resync circuit and refactor the CSR block, significantly reducing manual RTL coding time.
0:46:11 Python Modeling for Loop Optimization: A Python-based system model was generated to facilitate faster-than-RTL simulations. This model will be used for deterministic analysis of Costas loop gains and testing modem performance under Doppler shifts and low SNR environments.