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Porting Analog Designs: A Deep Dive into Automated Library Generation and ADC Porting

• 0:00:03 Introduction and Context: The video addresses a LinkedIn post regarding the shutdown of eFabless and the presenter's transition to the IHP PDK. The goal is to demonstrate the process of generating standard libraries and porting an ADC design. The presenter warns this is a highly specialized topic, and will focus on the step-by-step engineering.

• 0:01:11 Setting Up the Environment: The presenter shows his screen, adjusts terminal and text editor font sizes, and navigates to the ASX project directory (available on his GitHub).

• 0:01:30 Overview of the 'ASX' project Mentions that the 'ASX' project contains several IPs. Describes porting of an ADC originally created using 28nm technology, to Sky 130, which took place 3-4 years ago.

• 0:03:52 Introducing 'cic Creator': Explains that cic Creator, a tool he started writing around 2014, will be used for automatically generating the ADC.

• 0:04:20 Demonstrating the Ported Transistor Library: The presenter goes into a newly ported transistor library and shows its contents, including standard cells designed for analog designs (not for automatic place and route).

• 0:05:04 Standard Cells: details of the contents of the library are provided. These include tie cells, inverters, buffers, NAND/NOR gates, schmitt triggers, flipflops, resistors and capacitors.

• 0:06:11 Generated Schematics and Layout: Highlights that the schematics and layout are automatically generated by cic Creator and a transpiler, not hand-drawn.

• 0:07:08 Top-Level Layout Comparison: Compares the top-level layout of the IHP and Sky130 versions of the library, noting their similar sizes and different layout styles.

• 0:09:51 Layout Automation using a compiler. Explains that layout is automated with a self-written compiler, not drawn manually.

• 0:10:21 Examining the cic Directory: Shows the cic directory within the library folders, containing the configuration files for the automated generation.

• 0:10:58 File Comparison (Checksums): Uses shasum to compare files between the IHP and Sky130 versions, demonstrating that many files are identical or very similar.

• 0:12:05, 0:13:47 Investigating Differences Investigates the differences reported by a diff command. Many of the differences are negligible.

• 0:12:44 Technology-Independent Descriptions: Explains that the Digital.spy file, containing the circuit topology, is identical between the two technologies because it's technology-independent.

• 0:14:44 Components.json and Routing Instructions Explains that components.json provides instructions to cic Creator on how to perform circuit routing.

• 0:15:15, 0:18:18 Routing Inheritance: Details the recipe for describing the routing of an inverter. The description for routing is inherited across similar cell types (1x, 2x, 8x inverters).

• 0:19:53 Technology-Specific Files: Opens the ihp.tech and sky130.tech files, explaining that these files contain layer definitions and design rules specific to each technology.

• 0:22:09 Transistor deos File: Shows the deos file, containing ASCII art descriptions of the transistors, and highlights the differences between the IHP and Sky130 versions.

• 0:23:40 ASCII Art Describes the ASCII art used to represent the transistors and how the art is modified to accommodate technology-specific DRC rules.

• 0:27:38 Generating the Library: Demonstrates deleting the existing design files and regenerating the entire library (schematics, layout, symbols) using cic Creator and the transpiler.

• 0:31:31 cic Output File: Shows the large cic output file (JSON format) generated by cic Creator, containing detailed placement and routing information.

• 0:33:12 Transpiler (cic.py): Explains the role of the Python-based transpiler in converting the cic file into XSCHEM and Magic formats.

• 0:35:01 Porting a Transistor Library: Begins the process of porting a different transistor library to IHP, copying necessary files and modifying the technology file.

• 0:43:45 DRC Error Fixing: Starts addressing DRC errors in the newly generated layout, focusing on the NMOS transistor first.

• 0:45:49 Iterative DRC Fixing: Iteratively modifies the transistor ASCII art and technology rules to resolve DRC violations.

• 0:57:05 DRC Clean Transistors: Achieves DRC-clean status for both NMOS and PMOS transistors.

• 01:01:23 Top Level DRC Clean Check: Verifies that all versions are DRC clean.

• 01:02:23 LVS Clean Check Attempt: Attempts to check if the generated files are also LVS clean, but faces some difficulties.

• 01:05:40 Committing Changes: Commits the changes to the repository.

• 01:06:26 Simulation Setup: Discusses the next step of setting up simulations (which he hasn't done yet due to issues with running simulations on his Mac).

• 01:08:11 Porting the SAR ADC: Begins porting a 9-bit SAR ADC design to IHP.

• 01:10:34, 01:11:41, 01:15:57 Challenges and modifications. Faces issues with parasitic capacitors and metal resistors in the design. Makes changes to some of the metal resistor names.

• 01:17:21 Generated ADC Layout: Successfully generates the ADC layout in IHP.

• 01:17:53 Initial DRC Check: Surprisingly, the generated ADC layout has only 9 DRC errors.

• 01:18:43 Fixing DRC Errors in the ADC: Starts iteratively fixing DRC errors in the ADC layout, primarily related to metal spacing.

• 01:29:41 Modifying routing: Explains that ports can be moved around to accommodate routing problems.

• 01:36:47 DRC Clean ADC: Achieves a DRC-clean ADC layout after about half an hour of work.

• 01:37:55 8-bit ADC: Also generates an 8-bit version of the ADC, which is also DRC clean.

• 01:38:40 Size Comparison: Compares the sizes of the IHP and Sky130 versions of the 9-bit ADC, finding that the IHP version is surprisingly smaller.

• 01:42:52 Conclusion: Did not expect to port the ADC so fast.