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Abstract:
This lecture recording covers the third week of a digital design course. It begins by reviewing sequential logic concepts, including the definition and components of Finite State Machines (FSMs), the difference between latches and edge-triggered D flip-flops, and the necessity of flip-flops for reliable state holding in synchronous systems. The lecture details the design process for a Moore-type FSM using a "smart" traffic light controller example, covering state transition diagrams, state encoding (binary, one-hot, output-encoded), deriving next-state and output logic using truth tables and Boolean simplification, and basic timing considerations. Moore vs. Mealy FSMs are contrasted using a "smiling snail" sequence detector example.
The second part introduces the practical lab component of the course, focusing on Field-Programmable Gate Arrays (FPGAs). It explains FPGA structure (LUTs, switches, reconfigurability), their advantages/disadvantages compared to CPUs/ASICs, and their application in modern systems and research (including examples from the Safari research group like DRAM Bender). The specific lab board (Basys 3) is introduced, and the 10-lab sequence culminating in building a 32-bit MIPS microprocessor is outlined. The lecture concludes by introducing the need for Hardware Description Languages (HDLs) to manage design complexity, focusing on Verilog basics, including modules, ports, hierarchy, and multi-bit signal definition. The use of CAD tools like Xilinx Vivado for the FPGA design flow (synthesis, placement, routing, simulation) is also mentioned.
Lecture Recap: FSM Design, FPGAs, and Verilog Introduction
0:00:34 Recap of Previous Lecture: Reviewing sequential logic design and Finite State Machines (FSMs). Output depends on current inputs and past values (memory).
0:01:36 Combinational vs. Sequential Example: Standard combination lock vs. a sequential lock requiring a sequence (memory).
0:02:05 Finite State Machine (FSM) Definition: A model with a finite number of states, inputs, outputs, and defined transitions/output generation.
0:02:40 FSM Implementation Components: Requires a State Register (memory), Next-State Logic (combinational), and Output Logic (combinational).
0:03:45 State Register Requirements: Must capture the next state at the clock edge and hold the current state stable for the entire clock cycle for combinational logic evaluation.
0:04:18 Latches vs. Flip-Flops: Basic latches are "transparent" (output changes follow input while the clock is active), which is problematic for FSMs.
0:04:47 D Flip-Flop: An edge-triggered element that solves the transparency problem. It samples input (D) only on the clock edge (e.g., rising edge) and holds the output (Q) stable otherwise. Built using a master-slave latch structure.
0:07:08 D Flip-Flop Based Register: Multiple D flip-flops used in parallel to store multi-bit state values. Complexity noted (e.g., ~34 transistors per flip-flop).
Rule: Change state every 5s (clock cycle), unless an avenue has traffic and its light is green (it stays green - potential fairness issue noted).
0:12:55 FSM Structure: Requires Clock and Reset inputs. Reset state is crucial for defining the starting point.
0:13:45 Traffic Light FSM Diagram (Moore): Walkthrough of the 4 states (S0-S3) and transitions based on TA/TB inputs. Outputs (light colors) are shown inside the state circles, indicating a Moore machine.
0:17:56 State Transition Table: Converting the FSM diagram into a tabular format (Current State, Inputs -> Next State).
0:19:17 State Encoding: Assigning binary values to states (e.g., 00, 01, 10, 11 for 4 states). Requires log2(N) bits.
0:19:49 Deriving Next-State Logic: Using the encoded state table to create truth tables and Boolean expressions for the next state bits (S1', S0') as functions of current state (S1, S0) and inputs (TA, TB).
0:21:34 Deriving Output Logic (Moore): Creating truth tables and Boolean expressions for output bits (LA1, LA0, LB1, LB0) as functions only of the current state bits (S1, S0). Requires encoding outputs (R/Y/G) into binary.
0:23:39 FSM Schematic Implementation: Showing the synthesized combinational logic for next-state and output connected to the D flip-flop state register.
0:24:35 Timing Diagram & Considerations: Illustrates state changes synchronized to the clock edge. Introduces propagation delay in combinational logic. Key Takeaway: The clock period must be long enough to allow combinational logic to compute the next state/output before the next clock edge captures it. Asynchronous reset is mentioned.
Binary (Full): Uses the minimum number of flip-flops (log2 N). Logic complexity varies.
One-Hot: Uses N flip-flops (one per state). Often simplifies next-state/output logic but uses more state elements.
Output-Encoded: State bits directly represent outputs. Simplifies output logic (especially for Moore), but state representation might be less intuitive. Trade-offs depend on design goals.
0:33:26 Moore vs. Mealy Example: Smiling Snail: FSM to detect the input sequence "1101". Moore version requires 5 states; Mealy version achieves it with 4 states by having the output occur on the transition.
0:36:38 FSM Design Summary: Process involves defining states, diagramming transitions/outputs, encoding, deriving logic. Compared to programming but emphasizes hardware's stateful nature and concurrency. Hierarchy is used for complex systems.
0:40:58 Start of Part 2: Labs & FPGAs: Introduction to the practical lab sessions.
0:45:01 What is an FPGA?: Field-Programmable Gate Array - a reconfigurable hardware substrate with programmable logic blocks (LUTs), interconnects (switches), and I/O. Offers a balance between software flexibility and ASIC efficiency.
0:46:47 FPGA Applications: Used in diverse areas like deep learning, HPC, scientific computing, DNA sequencing, and research (Safari group examples: DRAM Bender/SoftMC for DRAM/memory studies, PIM prototypes).
0:55:19 Lab FPGA Board: Basys 3: Overview of the board's features (Artix-7 FPGA, USB, VGA, LEDs, switches, etc.).
0:56:21 Overall Lab Goal: To design and implement a 32-bit MIPS microprocessor on the FPGA board over 10 exercises.
0:57:11 Lab Exercise Outline: Brief description of Labs 1-9, progressing from basic circuits and FPGA I/O to FSMs, ALU design, simulation/testing, assembly programming, full processor integration, and performance analysis.
1:00:43 FPGA Internals: Key components are Lookup Tables (LUTs, e.g., 6-input) implementing combinational logic, and programmable switches/interconnects. Configuration is done via a bitstream loaded into on-chip SRAM. May include hardcoded blocks (multipliers, DSPs, processors) for efficiency.
1:05:01 FPGA Pros & Cons: Pros (Direct hardware implementation, high performance/efficiency vs. software, lower NRE cost/time-to-market vs. ASIC, reusability). Cons (Lower performance/efficiency vs. ASIC, overhead of programmability - area, latency, power, reliability concerns).
1:08:26 Computer-Aided Design (CAD) Tools: Essential for managing FPGA complexity. Automate synthesis (HDL to logic), placement (mapping logic to FPGA resources), routing (configuring interconnects), and bitstream generation.
1:10:00 Xilinx Vivado: The specific CAD tool suite used in the labs for simulation, synthesis, implementation, debugging, and programming the FPGA.
1:11:46 Introduction to Verilog (HDL): Motivation: Managing the complexity of modern chips (billions/trillions of transistors).
1:14:52 Why Hardware Description Languages (HDLs)?: Needed to describe hardware structures (wires, gates, registers, clocks), handle concurrency/parallelism inherent in hardware, and enable simulation and synthesis.
1:17:43 HDL Design Principles: Hierarchy (breaking designs into modules), Primitives (basic building blocks like gates), Top-Down and Bottom-Up design methodologies.
1:20:30 Verilog Basics - Modules: The fundamental building block. Defined using module ... endmodule, includes a name and a port list (inputs/outputs).
1:21:51 Verilog Basics - Multi-bit Signals: Declaring buses using range notation [MSB:LSB], e.g., input [31:0] data_bus;. Differentiates this from array declarations [0:31].