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Abstract:
This IEEE IFCS 2021 tutorial demonstrates a method for generating a precise hardware 1-PPS (one pulse per second) timing signal using a Software Defined Radio (SDR) processing Global Navigation Satellite System (GNSS) signals, specifically leveraging the open-source GNSS-SDR framework. The presentation outlines the challenges of obtaining accurate timing from SDR systems due to asynchronous data transfer and processing latencies. It identifies the ADC sampling clock as the only reliable time reference within the SDR chain. The core solution involves steering the frequency of the ADC's clock (which also clocks the FPGA) based on the timing corrections derived from the GNSS-SDR software's Position, Velocity, and Time (PVT) solution. An FPGA counter generates the physical 1-PPS pulse from this steered clock. The results show that this closed-loop system achieves timing stability (Allan Deviation) comparable to dedicated hardware GNSS receivers, reaching approximately 10⁻⁸ at 1 second and 10⁻¹² at 10,000 seconds. Potential pitfalls, such as sample drops caused by incorrect GNSS-SDR configuration and challenges with less stable oscillators like TCXOs, are discussed along with their solutions. While frequency stability is demonstrated, precise phase control remains an area for further investigation.
Generating a Hardware 1-PPS Signal from GNSS using Software Defined Radio
0:00 Goal: Generate a hardware 1-PPS timing signal from GNSS signals decoded using Software Defined Radio (SDR), specifically the GNSS-SDR framework.
0:20 SDR Principles: SDR minimizes hardware (antenna, LNA, frequency down-conversion, ADC) and performs signal processing in software on a general-purpose CPU, analyzing I/Q (complex) data. This allows flexibility, e.g., for spoofing/jamming analysis.
1:11 Control Objective: Use the time information derived from the GNSS signal by GNSS-SDR to steer the local oscillator of the SDR front-end.
2:03 Problem Statement - SDR Data Flow: SDR reception involves an antenna, preamp, and I/Q detector feeding dual ADCs (e.g., inside an AD9361 on an Ettus B210). Data goes through an FPGA to the CPU via asynchronous interfaces (USB/Ethernet).
3:37 Embedded Feasibility: Systems like Raspberry Pi 4 have sufficient processing power for this GNSS-SDR approach.
4:18 Problem Statement - Sample Timing: Asynchronous data transfer (USB, Ethernet) and variable processing delays mean the arrival time of data packets at the CPU doesn't reflect the precise sample acquisition time.
4:51 Key Insight - ADC Timestamp: The only reliable timing information comes from the ADC sampling instant. GNU Radio (used by GNSS-SDR) timestamps data blocks based on the ADC sample count.
5:10 Proposed Solution - Clock Steering: Steer the clock that drives the ADC and FPGA. Control this clock's frequency based on the timing error calculated by GNSS-SDR.
5:27 Hardware Implementation (1-PPS Generation): Implement a counter within the FPGA, clocked by the (now steered) ADC clock. The counter counts from 0 to Fs-1 (where Fs is the sampling frequency) to generate a 1-PPS output pulse.
5:48 Verification Setup: Use a high-precision time interval counter (HP 53132A) referenced to a Hydrogen Maser, comparing the SDR-generated 1-PPS against a hardware u-blox GNSS receiver's 1-PPS output.
6:26 Open Loop Results: Without control, the SDR's 1-PPS output drifts significantly relative to the reference, demonstrating the need for closed-loop steering.
7:26 Closed Loop Results: Steering the SDR's clock using the GNSS-SDR PVT solution keeps the 1-PPS output's timing error well within the target +/- 100 nanoseconds compared to the reference.
8:18 Sampling Rate Considerations: Using sampling frequencies that are integer fractions of the SDR's master clock is crucial to avoid frequency errors and drift.
9:03 Potential Issue - GNSS-SDR Conditioner: A specific configuration issue in the GNSS-SDR 'conditioner' block can lead to periodic sample drops, causing discrete phase steps (e.g., 500 ns every ~hour at 2 Msps). The fix is to use a "pass-through" configuration.
10:22 Corrected Closed Loop Performance: With the configuration fixed, the SDR-generated 1-PPS achieves excellent frequency stability, comparable to the hardware u-blox receiver (Allan Deviation ~10⁻⁸ @ 1s, decaying to ~10⁻¹² @ 10,000s).
11:44 Using Less Stable Oscillators (TCXO): Replacing a stable OCXO with a TCXO (common in embedded devices) shows similar performance is achievable, but requires careful control loop tuning and initialization.
12:32 TCXO Initialization: The large initial frequency error of a typical TCXO necessitates an initial frequency estimation phase before closing the loop to prevent instability.
13:23 Conclusion: The method successfully bridges software-derived GNSS timing to a physical hardware 1-PPS signal by steering the ADC clock. Frequency stability is high, but precise phase alignment requires further work. Sample loss impacts phase significantly.
14:16 Code Availability: A fork of GNSS-SDR implementing this functionality is available.