This evaluation analyzes Fable 5.2, an advanced AI-driven electronic design automation (EDA) tool used to redesign a legacy phase-locked loop (PLL) circuit. The primary objective was replacing an unstable high-$K_{\text{vco}}$ ring oscillator with a current-starved architecture suitable for a single tiny tapeout tile. Over a six-day workflow constrained by private Claude Pro token limits, the AI autonomously handled schematic generation, Python-scripted physical layout, design rule checking (DRC), layout-versus-schematic (LVS) verification, temperature-compensation bias design, and corner-case simulations. The final integrated design successfully locks and generates a 128 MHz output clock from an 8 MHz reference clock across process corners.
Key Highlights & Timestamps
0:00 Introduction: Overview of testing Fable 5.2 on a legacy "Sun PLL" featuring an operational amplifier-controlled VDD ring oscillator that suffered from extreme $K_{\text{vco}}$ sensitivity and slow-corner failure.
1:54 The first prompt: Initiating the redesign of the "ray PLL" by providing prompt instructions and lecture notes specifying a current-starved ring oscillator with capacitive loads and current mirrors.
4:58 The oscillator: Discovery of an AI-generated temperature compensation scheme utilizing a proportional-to-$V_{\text{GS}}$ bias circuit with a parallel resistor to stabilize oscillation frequency against thermal drift.
7:02 The first layout: Examining the Python code-generated physical layout, noting initial ground routing errors and the need to enforce modular unit-cell grouping for the inverter core.
7:53 Layout optimization: Compressing the layout area to fit strictly within a single tiny tapeout tile to minimize fabrication costs, managed under private Claude Pro token generation limits.
9:20 Simulation: Autonomous verification across process corners, revealing that layout parasitics reduced maximum speed and prompting an automated adjustment of feedback dividers to target 128 MHz.
12:15 The Schematic: Reviewing the complete PLL architecture comprising a phase frequency detector, charge pump, and type-II loop filter with resistors integrated beneath metal-insulator-metal (MIM) capacitors.
14:13 The Bias: Detailed breakdown of the generated startup and biasing circuit, which establishes a gate-source voltage referenced current proportional to $V_{\text{GS}}$ divided by resistance ($V_{\text{GS}}/R$).
18:07 The Layout: Inspection of the top-level layout integrated inside the tiny tapeout tile, highlighting the incorporation of end diodes derived from previous reference designs.
20:05 The Simulations: Post-layout transient simulation analysis demonstrating stable locking across process corners using automated, corner-specific digital trim codes (codes 3, 4, and 6).
Glossary
PLL (Phase-Locked Loop): A control system that generates an output signal whose phase is locked to the phase of an input reference signal, widely used for frequency synthesis and clock generation.
Ring Oscillator: An oscillator circuit composed of an odd number of inverters connected in a feedback loop, where frequency is determined by propagation delay per stage.
DRC (Design Rule Checking): An EDA verification software process ensuring that a physical integrated circuit layout complies with specific semiconductor fabrication foundry rules.
LVS (Layout Versus Schematic): An EDA verification step checking that the physical layout netlist precisely matches the electrical schematic netlist.
$K_{\text{vco}}$ (VCO Gain): The sensitivity of a voltage-controlled oscillator, measured as the change in output frequency per unit change in control voltage ($\text{Hz/V}$).
Process Corners: Variations in semiconductor fabrication parameters (slow, typical, fast) used to simulate and verify circuit robustness under worst-case operating extremes.
MIM Capacitor (Metal-Insulator-Metal Capacitor): High-density integrated capacitors constructed between two parallel metal layers, frequently deployed in analog loop filters.
$V_{\text{GS}}$ (Gate-Source Voltage): The voltage potential applied between the gate and source terminals of a field-effect transistor.
Trim Code: Digital configuration bits used to adjust internal circuit parameters (such as bias current or switched capacitance) to compensate for manufacturing process variations.