This Chips and Cheese article provides a deep-dive microarchitectural analysis of Zhaoxin's KX-7000 processor, featuring the new "Century Avenue" core architecture. The KX-7000, an 8-core chiplet-based design likely built on a 16nm process, represents a significant step up from Zhaoxin's previous "LuJiaZui" cores, aiming for higher performance relevant to modern applications. Century Avenue is a 4-wide out-of-order core achieving 3.2 GHz, offering substantial single-threaded gains over its predecessor and roughly matching the performance level of AMD's 2011 Bulldozer architecture. It features surprisingly powerful FMA execution units but is hampered by an inefficient AVX2 implementation (splitting 256-bit ops into 128-bit uops), high frontend latency (especially for branches), a relatively small L2 cache compared to its high L3 latency, and critically poor DRAM performance in terms of latency, read bandwidth, and fairness between cores. While a notable effort towards China's goal of domestic chip production, the KX-7000 lacks the balance, sophistication, and overall performance of contemporary or even decade-old western designs. Hacker News commenters echo this, highlighting the Bulldozer-era performance, severe memory subsystem and power efficiency issues, while also discussing its strategic importance for China as a domestic alternative and the common role of government support in such Chinese tech ventures.
Zhaoxin KX-7000 CPU Analysis & Discussion Summary
Chips and Cheese Article Summary:
Introduction & Context:
Zhaoxin is a Chinese x86 CPU designer, a joint venture between VIA Technologies (inheriting its x86-64 license) and the Shanghai government.
The KaiXian KX-7000 CPU features the new "Century Avenue" architecture, aiming to fix the performance inadequacy of the previous "LuJiaZui" (KX-6640MA).
Core Overview ("Century Avenue"):
A 4-wide decode/dispatch core with AVX2 capability and improved Out-of-Order execution window (192-entry ROB).
Targets higher clocks: Observed running at 3.2 GHz (specs claim up to 3.7 GHz).
Chiplet design: 8 cores on one die with a shared 32MB L3 cache, plus a separate IO die (similar to single-CCD Ryzen).
Process Node: Unspecified, rumored to be 16nm.
Frontend Analysis:
Features a 64KB L1 instruction cache feeding a 4-wide decoder; conventional design (no op cache or loop buffer).
Instruction fetch bandwidth bottlenecks quickly when missing L1i.
Branch Prediction: Improved direction predictor, but high taken branch latency (~3 cycles) due to a simple BTB tied to L1i. A regression from LuJiaZui's zero-bubble capability. No branch fusion.
Backend & Execution:
Uses a Physical Register File (PRF) scheme, an improvement over LuJiaZui's ROB-based design.
Features large, semi-unified schedulers.
Execution Units: 3 ALUs (fast 2-cycle 64-bit integer multiply). Surprisingly strong FP/vector side with 2x 256-bit FMA throughput per cycle (matching Haswell).
AVX2 Implementation Flaw: Despite high FMA throughput, all 256-bit operations are split into two 128-bit micro-ops, consuming double the resources (ROB, schedulers, registers, load/store queues), hindering effective performance.
Memory Subsystem:
L1 Data Cache: 32KB, 8-way, 4-cycle latency. Only supports 1x 128-bit store per cycle, limiting 256-bit store bandwidth.
DRAM Performance: Critically poor. Very high latency (>200ns). Low achieved bandwidth (system trained only to 1600 MT/s), especially for reads (<12 GB/s), likely limited by latency/queues. Poor fairness between cores under load (latency skyrockets).
Performance:
Single-Threaded (SPEC CPU2017): Massive gain over LuJiaZui. Roughly equivalent to AMD's FX-8150 (Bulldozer), slightly behind in integer, slightly ahead in FP. Far behind modern cores.
Multi-Threaded: Mixed results, often losing to the 8-core/4-module Bulldozer FX-8150 and quad-core Skylake i5-6600K in tasks like encoding (libx264) and compression (7-Zip). Does better in Y-Cruncher (AVX2) and OpenSSL RSA. Overall unimpressive.
Conclusion:
KX-7000 is a significant step for Zhaoxin towards usable domestic CPUs for China.
However, the design feels unbalanced and lacks sophistication (poor frontend, inefficient AVX2, terrible memory subsystem). It tries to make parts bigger without a cohesive, efficient design.
Performance lands around decade-old western CPUs, highlighting the long road ahead.
Hacker News Discussion Summary:
Performance Level:
Commenters agree the performance is roughly equivalent to 2010/2011 AMD Bulldozer or Intel Sandy/Ivy Bridge.
Seen as "a long way to go" but potentially only "2 revs away" from being sufficient for certain tasks (like hosting AI accelerators).
Key Criticisms:
Memory subsystem performance (latency, bandwidth, fairness) is highlighted as extremely poor and unacceptable for modern client CPUs.
Power efficiency is noted as dismal based on other reviews (PCWatch), consuming similar power to a Ryzen 5 5600G for 1/3 the performance in Cinebench MT, with high idle power.
Reviewer (Chester Lam / clamchowder) confirmed memory training issues during testing (only reaching 1600 MT/s) and system instability.
Strategic Importance for China:
Viewed primarily as a strategic "insurance policy" against potential cutoffs from AMD/Intel, ensuring domestic supply and control over firmware (security).
Government involvement (JV with Shanghai govt.) is seen as typical for bootstrapping strategic industries in China, potentially mandating purchases by state entities regardless of competitiveness.
Technical Heritage & Alternatives:
Debate on whether the VIA x86 license heritage helps or hinders Zhaoxin compared to potentially cleaner-slate approaches (like RISC-V or other Chinese designs adding x86 translation).
Some mention competent Chinese RISC-V CPUs might already be faster, even when emulating x86.
Security & Openness:
Some users muse about the lack of Intel ME, while others counter with concerns about potential unknown Chinese government backdoors ("out of the frying pan, into the fire").