This video presents an in-depth teardown and analysis of a Tesla Model Y indoor cabin radar module. The investigation examines the module's external and internal construction, PCB layout focusing on RF and power management sections, and culminates in a detailed die-level analysis of the Texas Instruments 60 GHz radar System-on-Chip (SOC). A variety of analytical techniques are employed, including X-ray imaging of the SOC package, X-ray Fluorescence (XRF) to determine PCB trace surface finish (revealing a thin silver immersion), Raman spectroscopy to identify the radome material (polycarbonate), and extensive optical and Differential Interference Contrast (DIC) microscopy of the SOC die. The analysis reveals a single PCB design featuring patch antennas isolated by Electromagnetic Band Gap (EBG) structures. The TI SOC, identified as being on a 45nm RF CMOS process, showcases a complex architecture with three transmitters and four receivers, a 20 GHz synthesizer whose output is tripled, integrated phase shifters for MIMO/beamforming, I/Q downconversion, extensive built-in self-test (BIST) paths, and on-chip DSP and Cortex processing cores.
Deep Dive into Tesla's Model Y Cabin Radar: From PCB to Die
00:00:09 Introduction to the Teardown: The video will conduct a deep analysis of a Tesla Model Y indoor cabin radar module, examining its components down to the integrated circuit. This analysis is independent, based on publicly available information and direct observation.
00:01:35 External Module Examination: The module features a single interface for power and data (likely CAN bus or Ethernet), a plastic radome, and a metal heatsink body. It's designed for indoor use, with less stringent environmental requirements than external automotive radars.
00:03:35 Initial Disassembly and PCB Overview: The module houses a single PCB. The back cover removal reveals thermal pads for heat dissipation from components like power converters and the main SOC to the metal casing.
00:04:37 PCB Backside (Power & Control): This side contains DCDC converters (including a TI quad buck converter), passive components, and thermal vias to draw heat from the radar SOC on the other side. A memory chip, likely for calibration or firmware, is also present.
00:06:03 PCB Frontside (RF Section): The core is a Texas Instruments 60 GHz SOC radar chipset (3 transmitters, 4 receivers). The PCB features patch antennas. Co-planar waveguide feeds from the SOC transition to striplines leading to the patch antennas.
00:07:38 Antenna and Isolation Design: Single patch antennas provide broad coverage suitable for cabin monitoring. Electromagnetic Band Gap (EBG) structures are implemented between antennas to enhance isolation and prevent surface wave propagation between transmit and receive elements. The SOC itself is housed under a metal shield for further isolation.
00:10:18 SOC Package and Footprint: The TI SOC utilizes a complex BGA package with dedicated RF launch structures (vertical coaxial transitions to co-planar waveguides) and extensive grounding for its multiple RF ports.
X-Ray Fluorescence (XRF) on the PCB traces indicates a very thin silver immersion finish over copper.
Raman spectroscopy identifies the black radome material as polycarbonate, a cost-effective choice though not optimal for RF performance.
00:17:15 SOC Architecture (Based on Block Diagram & Die): The TI radar SOC is a highly integrated 60 GHz FMCW radar solution.
RF Front-End: It includes three transmit (TX) channels with phase shifters (supporting MIMO and beamforming) and four receive (RX) channels with LNAs and I/Q downconversion mixers.
Synthesizer: A 20 GHz synthesizer (with a ramp generator for FMCW) has its output frequency tripled to achieve the 60-64 GHz operating range.
Processing: The SOC integrates a Cortex processor, a DSP core, and memory for on-chip radar signal processing.
Calibration: Extensive Built-In Self-Test (BIST) and calibration features are evident, with signal paths allowing PA outputs to be routed to LNA inputs for loopback testing.
00:21:55 Die Examination (TI 45nm RF CMOS): Microscopic examination of the decapsulated die reveals the physical layout of the functional blocks.
PLL & Synthesizer: Distinct VCO cores for the 20 GHz synthesizer and cleanup PLL are visible, along with associated passive components like large inductors. The frequency tripler section is also identified.
TX Chain: Each PA chain includes phase shifters, multiple amplification stages (ultimately four PAs combined per channel), and output power combiners with transformer coupling to a single-ended output. Directional couplers for power detection are also present.
RX Chain: LNAs, quadrature LO generation for I/Q mixers, and IF sections are laid out.
LO Distribution: A network of splitters and buffers distributes the 60 GHz LO signal to all TX and RX channels.
Digital Core: A large area of the die is dedicated to the digital processing (DSP, CPU, memory), which is obscured by top metal layers.
00:36:06 DIC Microscopy: Differential Interference Contrast microscopy highlights surface features, metal roughness, and damage from the decapsulation process, offering alternative views of the die structures.