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Abstract:

This video provides an overview of TSMC's latest technology roadmap presented at their Tech Symposium, highlighting innovations beyond simple transistor scaling. The roadmap details the progression from the current N3 node to N2 (nanosheet, H2 2025 production), N2P (2026), A16 (featuring Backside Power Delivery Network or Super Power Rail, H2 2026), and the newly announced A14 (2028), all promising significant performance, power efficiency, and density improvements. The presentation also covers advanced packaging technologies like die stacking (SOIC, hybrid bonding, bumpless stacking) and wafer-scale integration (Sysmon Wafer, launching 2027 for AI), alongside solutions for managing the high power demands of future chips, including integrated power management ICs, inductors, and capacitors. TSMC reports strong customer adoption for N2 and anticipates the US semiconductor market doubling by 2030, positioning their multi-faceted scaling approach and US fabs (like Fab 21) to meet future demand across various market segments.

TSMC Technology Roadmap Overview

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