This presentation by Guraj Seshwar, Assistant Professor at the University of Toronto, argues that robustly mitigating hardware vulnerabilities like Spectre and Rowhammer in future systems requires not just good defenses, but also effective offensive tools applied at the design stage. The talk introduces "Amulet," a novel tool that extends black-box fuzzing techniques to microarchitectural simulators, enabling the early detection of speculative leakages in CPU counter-measures. Amulet successfully uncovered previously unknown vulnerabilities in multiple leading Spectre defenses in minutes to seconds, demonstrating the efficacy of systematic testing at design time.
The presentation then shifts focus to Rowhammer, specifically addressing the Per-Row Activation Counting (P-RAC) mitigation proposed by JEDEC. It reveals a critical vulnerability, the "Fill and Escape" attack, against existing P-RAC implementations that exploit a time gap between alert and mitigation. To counter this, a new practical and secure implementation called "QRA" (Quality-of-Service-aware Row Activation counting) is proposed, utilizing a priority queue to ensure heavily activated rows are prioritized for mitigation. Finally, the talk highlights a new class of side-channel and covert-channel attacks enabled by P-RAC's all-bank refresh signals, allowing an attacker to deduce precise victim memory activity. Simple timing-independent mitigation strategies are suggested to address these new information leakages, emphasizing the continuous need for an offensive mindset in designing future hardware security.
Robustly Mitigating Spectre and Rowhammer in Future Systems
0:41 Importance of Offensive Mindset: Robustly mitigating hardware vulnerabilities like Spectre and Rowhammer requires developing strong offensive tools for early detection at the design stage, rather than solely focusing on defensive measures.
2:00 Introducing Amulet for Spectre Detection: Amulet is a novel tool designed to detect speculative leakages in microarchitectural defenses during the early design phase, specifically within CPU simulators. This addresses the critical need to identify vulnerabilities before hardware commercialization.
11:57 Amulet's Methodology: The tool utilizes random test programs and compares expected leakage (from an emulator) with observed microarchitectural traces (from a simulator) to identify unexpected information leakages.
15:13 Amulet's Innovations: To overcome challenges posed by simulator slowness and vast state spaces, Amulet optimizes testing speed (12x faster by injecting tests into a continuously running simulator) and amplifies detection by artificially reducing microarchitectural structure sizes.
20:26 Amulet's Findings: Amulet successfully identified 3 previously known and 6 new, unknown speculative leakages across four popular microarchitectural defenses (dating from 2018-2024), often detecting them within seconds. Vulnerabilities included unimplemented protections, implementation bugs, undocumented performance optimizations, and fundamental design issues.
34:20 Rowhammer and JEDEC's P-RAC: The talk addresses the Rowhammer problem, where repeated memory accesses cause bit flips in neighboring DRAM rows. It introduces JEDEC's Per-Row Activation Counting (P-RAC) as a major mitigation change, which involves counters per DRAM row signaling alerts to the CPU for targeted mitigations.
36:09 P-RAC Vulnerability: The tABBO_ACT Gap: A crucial flaw in P-RAC is the 180-nanosecond tABBO_ACT time gap between a DRAM alert and CPU mitigation, allowing attackers to perform additional activations and weaponize the defense.
40:13 "Fill and Escape" Attack: This new attack against FIFO queue-based P-RAC implementations (like Panopticon) exploits the tABBO_ACT gap. Attackers fill the mitigation queue with dummy rows, then hammer a target row during the gap, preventing it from being enqueued and thus mitigated.
43:09 QRA - A Secure P-RAC Implementation: The proposed solution, QRA (Quality-of-Service-aware Row Activation counting), uses a priority queue that tracks both addresses and their activation counts. This ensures heavily hammered rows are always prioritized for mitigation, preventing "Fill and Escape" and supporting future low Rowhammer thresholds.
46:31 QRA Performance Optimizations: QRA includes optimizations like opportunistic mitigations (other banks mitigating their high-priority rows when one alerts) and proactive mitigations on refresh intervals, significantly reducing performance overheads to near negligible levels.
1:01:35 New Side/Covert Channels from P-RAC: An upcoming work at ISCA demonstrates that P-RAC's all-bank RFMs (mitigations) are visible across the system, creating a powerful side channel. Attackers can observe latency spikes to deduce precise victim memory access counts and even extract secret key bytes (e.g., from AES T-tables) or establish high-bandwidth covert channels (10-100 kbps).
1:08:54 Defenses for New Side Channels: Simple, timing-independent mitigation strategies are proposed where the memory controller sends mitigations at a fixed or variable rate, decoupled from victim activity. These, combined with proactive mitigations, can limit information leakage with minimal performance impact.
1:10:00 Key Takeaways: Security must be considered at the hardware design stage to prevent vulnerabilities from being commercialized. Adopting an offensive mindset during design helps anticipate and address potential weaknesses, leading to more robust and long-lasting security solutions.