This article details AMD's pre-Zen interconnect architecture, specifically focusing on the "Trinity" Accelerated Processing Unit (APU) from 2012 and its unique approach to integrating CPU and GPU memory access. It examines Trinity's Northbridge-based design, which predates the ubiquitous Infinity Fabric. The author explores two distinct links for GPU-side memory access: "Garlic," a high-bandwidth, non-coherent path optimized for GPU workloads that bypasses CPU caches, and "Onion," a lower-bandwidth, coherent path enabling zero-copy data sharing with CPU memory. The analysis also covers the performance implications of CPU access to GPU memory, showing significant penalties due to uncacheable access. Through real-world workload testing, the article demonstrates that while Trinity's interconnect was a compromise lacking the seamless integration of modern designs, it proved sufficient for delivering powerful iGPU performance in its era, particularly for graphics-heavy applications, despite its inherent architectural "awkwardness" compared to contemporary Intel solutions.
Exploring AMD’s Pre-Zen Interconnect: A Deep Dive into Trinity’s Northbridge
0:00 Evolution of AMD Interconnects: Discussion of AMD's modern Infinity Fabric and its contrast with the earlier Northbridge architecture, which moved chipset functionality onto the CPU die.
0:40 Trinity APU Details: Introduction of "Trinity," AMD's 2012 APU, featuring Piledriver CPU modules and a Terascale 3 iGPU, specifically testing the A8-5600K variant.
1:10 Northbridge Architecture: The Northbridge operates on a separate voltage/frequency domain (1.8 GHz) and uses a two-level crossbar system (SRI and XBAR) to route requests to I/O and memory.
2:20 Dedicated GPU Memory Controller (GMC): Trinity’s iGPU has its own GMC, which arbitrates and schedules requests to maximize DRAM bandwidth, akin to the CPU's Memory Controller (MCT).
2:50 The "Garlic" Link (Radeon Memory Bus): This high-bandwidth link allows the GPU to saturate DRAM directly, bypassing the MCT and CPU cache coherency mechanisms, which is efficient as CPUs and GPUs typically don't share large amounts of data.
3:40 Controlled CPU Latency: Even under high GPU bandwidth demands (over 24 GB/s via "Garlic"), CPU memory latency remains well-controlled (under 120 ns), suggesting contention is more at the SRI/XBAR than at the DRAM controllers.
4:30 The "Onion" Link (Coherent Control Link): This link enables coherent access for the GPU to CPU-side cacheable host memory. However, it's bandwidth-limited (under 10 GB/s) and generates high probe traffic due to the lack of probe filters.
5:50 CPU Access to GPU Memory: When the CPU accesses GPU memory mapped into its address space (via "Garlic"), it becomes uncacheable (write-combining) from the CPU side, leading to significant performance penalties and reduced memory level parallelism.
7:20 Real-World Workload Analysis: Performance testing with benchmarks like Unigine Valley, Final Fantasy 14 Heavensward, The Elder Scrolls Online, RawTherapee, and Darktable demonstrates how different workloads utilize CPU vs. iGPU memory bandwidth.
11:00 Architectural Compromises: Trinity's "Garlic" and "Onion" links were a compromise solution that, while enabling zero-copy behavior, resulted in performance penalties when the CPU and GPU accessed each other's memory spaces.
11:30 Sufficiency for its Time: Despite architectural "awkwardness" compared to Intel's contemporary ring bus, Trinity's interconnect was sufficient for delivering powerful iGPU performance, with its weaknesses not significantly impacting graphics workloads due to high DRAM traffic demands.