This lecture provides a fundamental, simplified overview of the CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit fabrication process. It systematically outlines the key sequential steps involved in building a CMOS circuit, starting from initial wafer preparation, through the creation of doped wells (N-wells, P-wells) and active device areas. The core process of forming the polysilicon gate and doping the source/drain regions to construct transistors is detailed. The lecture then explains the crucial multi-layer metallization steps, including contact hole formation and interconnect wiring, necessary to connect millions or billions of transistors into functional circuits, concluding with the final passivation and bonding pad creation. This provides essential context for understanding how individual process steps contribute to the overall semiconductor manufacturing flow.
Exploring the CMOS Process Flow: From Wafer to Circuit
0:00 Introduction to CMOS Process Flow: This lecture offers a basic, simplified overview of the typical CMOS process flow, focusing on how different chemical process steps combine to create a functional circuit.
1:01 Wafer Preparation (Step Zero): Initial steps include laser scribing unique ID numbers (sometimes barcodes) on the back of the wafers, thorough cleaning, "gettering" (implanting imperfections on the back to attract defects away from the active surface), and establishing zero-layer alignment marks for subsequent patterning.
1:37 Well Formation (Step One): N-wells and P-wells are created through patterning, dopant implantation (e.g., phosphorus for N-wells), and diffusion. These wells define the regions of the wafer where specific types of devices will be formed, with modern processes typically utilizing both N-wells and P-wells.
2:03 Active Area Definition: Regions where transistors will be built are defined and isolated by growing thick oxide layers in non-active areas, ensuring electrical isolation between adjacent active regions. This is achieved through processes like local oxidation of silicon (LOCOS) or, more commonly today, shallow trench isolation (STI).
2:24 Polysilicon Gate Formation: A thin oxide layer is grown/deposited over the active areas, followed by the deposition and patterning of polysilicon to form the gates of the MOS transistors. Gate engineering, such as the creation of lightly doped drains (LDD) with sidewall spacers, is performed to optimize device performance.
2:47 Source/Drain Implantation and Diffusion: The main source and drain regions are created through ion implantation and diffusion. This involves separate steps for N-channel devices (using N-type dopants like arsenic) and P-channel devices (using P-type dopants like boron), with the polysilicon gate acting as a "self-aligned" mask to prevent dopants from entering the channel region. At this point, the basic transistor structure is complete.
2:54 Connecting Transistors: Contacts and Metallization: To connect the newly formed transistors, salicide layers (to improve contact resistance) are typically formed, followed by the deposition of an insulating oxide layer. Contact holes are then patterned and etched into this oxide, which are filled with conductive material (e.g., tungsten plugs in modern processes) to make electrical contact with the source, drain, and gate.
3:12 Multi-Layer Interconnects: Multiple layers of metal (commonly 2 to 10 layers, often copper in modern designs) are sequentially deposited and patterned to create interconnecting wires. Vias are used to establish connections between different metal layers, allowing for the complex wiring required to link millions or billions of transistors in a circuit.
3:42 Passivation Layer: A final protective passivation layer is deposited over the entire chip, except for specific regions where openings are created for bonding pads. These pads facilitate electrical connections to the external packaging, allowing the chip to communicate with other components.
9:45 Identifying a Transistor in Design: From a top-down design view, a transistor is identified wherever a polysilicon gate crosses an active area (diffusion region), with the source and drain regions implicitly located on either side of the gate within that active area.
12:15 Context for Future Studies: This lecture serves as an introductory overview, providing a coherent picture of how all the individual process steps fit together to form a CMOS device and circuit. Subsequent lectures will delve into the details of each unit process step.