This video chronicles the ambitious multi-month journey of building a 160-core RISC-V supercluster, cleverly disguised within an M.2 form factor. The project revisits earlier work on multi-core clusters, aiming for higher density and lower cost using edge connectors. The creator details significant challenges encountered during the design, manual assembly of tiny components, and extensive debugging of communication and power issues. Key problems included current leakage during programming, limitations of specific GPIO pins, and signal integrity issues on the open-drain bus requiring software workarounds. Despite numerous setbacks, the project culminates in a fully functional, power-efficient cluster. Demonstrations include a basic ray tracer (bottlenecked by serial communication) and a SHA-256 hashing benchmark, where the 160 low-power cores collectively outperform an 8-core desktop CPU. The video emphasizes the valuable lessons learned through persistent problem-solving.
Building a 160-Core RISC-V Supercluster: Design, Debugging, and Performance
0:00 Project Introduction: The creator unveils a 160-core RISC-V supercluster, designed to resemble a heavily modified SSD.
0:28 Inspiration & Evolution: The project builds upon a previous 256-core mega cluster, aiming to overcome past challenges with densely packed pin headers by utilizing M.2 edge connectors for better cost and density.
1:49 Modular Design: The supercluster features a main board with 10 vertical M.2 slots, each designed to hold a modular board containing multiple MCUs.
2:08 Compact MCU Modules: Each module is a 22x26mm, 4-layer PCB, meticulously designed with 16 MCUs, 64 components, and hair-thin traces to maximize density and stay within budget.
3:05 Assembly Challenges: Manual assembly of the vertical M.2 connectors proved extremely difficult due to unreachable pins, requiring custom soldering techniques.
4:25 Programming Issues & Fixes: Initial attempts to program individual MCUs led to current leakage and random heating due to shared bus lines. The solution involved powering all MCUs simultaneously and later repurposing GPIO pins to ensure proper programming.
6:09 Unique MCU Indexing: Each MCU is pre-programmed with a fixed index corresponding to its physical position, allowing for debugging and use as a 3D LED matrix.
8:08 Ray Tracing Implementation: The cluster was tested with a ray tracer, where each MCU would render a pixel. This highlighted the RISC-V cores' rudimentary instruction set (no floating point, square root, or integer multiplication/division).
High current draw from initial LED resistors caused crashes. Switching to internal pull-ups for LEDs significantly reduced current.
Using more than one module caused crashes, traced to limitations of specific GPIO pins (C13-15) and insufficient signal strength on the open-drain bus.
Weak 10k pull-up resistors on the bus caused slow signal rise times and data corruption; a compromise involved adding a delay on the host side.
12:33 Full System Functionality: After extensive debugging, including fixing cold solder joints, the cluster finally became fully functional.
13:00 Performance Bottleneck: The main limitation for the ray tracer's speed was identified as the slow 115 kilobits per second serial port, though the interface chip supports up to 8 megabits per second.
13:28 SHA-256 Hashing Benchmark: The cluster was benchmarked with a SHA-256 hashing algorithm, a computationally intensive task.
13:41 Impressive Performance & Efficiency: The 160 MCUs combined outperformed an 8-core desktop CPU in SHA-256 hashing while drawing under 4W (7mA per core at 3.3V), demonstrating remarkable power efficiency.
13:57 Conclusion & Lessons Learned: The project, despite its many failures and emotional challenges, yielded significant lessons and a rewarding outcome. Design files and code are available for others to learn from.