This video details the expansion of a previous RISC-V "supercluster" project into a modular "mega cluster" with 256 microcontrollers. The creator initially planned a single large board but opted for a hierarchical design using intermediate "cluster blades," each managing two superclusters, and a main baseboard. A key challenge arose with the omission of a dedicated command line for the higher-level bus connecting the blades. The creator ingeniously adapted the bus protocol by repurposing the clock signal to indicate bus activity and developed a robust collision detection and resolution mechanism, including randomized delays and unique ID broadcasting. The video demonstrates the successful assembly of the modular system, initial mesmerizing LED blinking, and a detailed explanation and live test of the refined bus communication protocol, showcasing its ability to handle multiple MCUs and detect collisions. The project is sponsored by JLC PCB.
Building a RISC-V Mega Cluster: Design, Challenges, and a Resilient Bus Protocol
0:02 Project Origin: The creator revisits a year-old project: a RISC-V "supercluster" composed of 16 low-cost RISC-V microcontrollers (MCUs) interconnected by an 8-bit bus, each with a pink LED for visualization.
0:30 Mega Cluster Vision: The long-term goal was to create a "mega cluster" by tiling multiple supercluster modules, arranged to display text and utilize general-purpose IO (GPIO) expansions.
0:50 Initial Design Hurdles: A massive single-board design for 16 superclusters proved too complex and risky to manufacture due to potential errors.
1:15 Modular "Cluster Blade" Design: An intermediate "cluster blade" board was designed, featuring two larger microcontrollers that each manage one supercluster, optimizing for GPIO expansion.
1:30 Hierarchical Bus Architecture: To avoid bus overcrowding (256 MCUs total), a tiered bus system was implemented:
Each supercluster has its own bus controlled by the two larger MCUs on the blade.
These larger blade MCUs are connected to a second 8-bit bus.
A "Mega cluster blade base" board includes a host microcontroller connected to the second bus, interfacing with USB.
The second bus operates at higher clock speeds due to the faster blade MCUs.
2:30 Sponsorship and Manufacturing: Boards were ordered from JLC PCB, highlighting their straightforward ordering process, color options (black chosen to emphasize LEDs), affordability, and additional services like 3D printing and CNC.
3:30 Assembly Process: The creator manually assembled all the components, including the individual superclusters, the cluster blades, and the baseboard.
5:13 Initial Power-On and Observation: Upon assembly, the system displayed mesmerizing simultaneous blinking LEDs, though internal oscillator drift caused them to desynchronize over time.
5:48 Critical Design Flaw Discovered: A major problem was identified: the second bus connecting the blade MCUs lacked a dedicated "command" line, which was a core part of the original bus protocol.
6:50 Bus Protocol Adaptation: The command line function was ingeniously integrated into the clock signal: an idle clock indicates a free bus, and the first low pulse of the clock signifies the start of a message.
Collision detection was maintained by reading back data at the rising edge after setting it at the falling edge; differing data indicates a collision.
Collision resolution involves adding a random waiting time before re-sending a packet to prevent immediate re-collisions.
To prevent undetected collisions when two processors send identical data, the unique 8-byte processor ID is sent at the beginning of each packet.
A checksum (XOR of all bytes) is added for data validation.
9:04 Live Testing Success: The revised bus protocol was successfully tested live with nine MCUs on a single bus, demonstrating effective collision handling and successful handshake packet transmissions.
9:54 Conclusion and Future Plans: The creator successfully overcame the design difficulties, implying future content will showcase the full potential of the mega cluster.