This episode of the "Open-Source Silicon Stream," hosted by Matt Van and featuring guest Mike Bell ("Rebel Mike"), provides a comprehensive update on the open-source silicon ecosystem and announces a new peripheral design competition. The stream covers recent developments, including the ongoing collaboration with Swiss Chips for IHP 130nm process shuttles, initial funding for Global Foundries 180nm support, and new features for the online chip viewer (3D exploration and decap imaging). The main highlight is the launch of a competition inviting participants to design Verilog-only peripherals for Mike Bell's Tiny QV RISC-V microcontroller. Two peripheral templates are provided (byte-level and full 32-bit), and submissions will be integrated into a collective microcontroller tape-out. The competition emphasizes collaboration, offers free entry with cool prizes, and has a six-week submission window. Discussions also delve into technical aspects like I/O multiplexing, size constraints, analog design limitations, and the possibility of pre-silicon judging using FPGA test boards.
Open-Source Silicon Stream: Tiny Tape Out Peripheral Competition
0:00 Stream Introduction: Host Matt Van introduces episode 17 of the "Open-Source Silicon Stream," focusing on open-source EDA and ASIC design, community building, and news.
0:22 Special Guest Mike Bell: Mike Bell, also known as "Rebel Mike" (creator of the Tiny QV RISC-V CPU), joins the stream to discuss the new competition.
2:19 Swiss Chips Partnership & IHP Shuttle: Matt provides an update on Swiss Chips, who are adding IHP 130nm process support to Tiny Tape Out. Two test shuttles have run, and one is currently open. He also visited the IHP factory clean room.
4:42 Current Tiny Tape Out Shuttle Dates: The IHP shuttle has 49 days remaining, and the Skywater shuttle (via chipfoundry.io) tapes out in 63 days.
5:10 Efabless Shutdown Refunds: Instructions are provided for claiming coupons or refunds due to the efabless shutdown (email claimtape.com).
5:31 Global Foundries 180nm Support Funded: Initial work has begun to support Global Foundries 180nm process, sponsored by Titus (makers of the T-key open-source security key), enhancing supply chain resilience.
6:40 Advanced Chip Viewer Features: Alexander Morvinc updated the chip viewer with 3D zoom, pan, and rotate for designs, and Tiny Tape Out 7 decap imaging now integrates microscope layers with GDS views and project links.
9:39 ORCONF 2025 Registration Open: Registration and talk submissions are open for ORCONF 2025 in Valencia, Spain.
11:39 Tiny Tape Out Peripheral Competition Announced: A new competition is launched for designing Verilog peripherals for Mike Bell's Tiny QV RISC-V microcontroller.
13:04 Tiny QV Microcontroller Background: Mike discusses his Tiny QV (4 tiles on Tiny Tape Out 6), a 4-bit serial RISC-V CPU running MicroPython with SPI interface for SD cards, noting a past UART bug workaround.
14:35 Competition Origin & Goal: The competition aims to foster collaboration by allowing participants to integrate their useful Verilog peripherals into the Tiny QV system, expanding its ecosystem.
16:57 Competition Logistics: Submissions are Verilog-only, via pull requests to the TT Sky25A-TinyQV GitHub repo. The target tape-out is Sky 25A (Sept 1st deadline) and potentially IHP. Free entry is offered, but physical dev kits are purchased separately.
24:17 Peripheral Templates: Two templates are available: a "byte" peripheral (single tile, 4-bit address, 16 bytes address space) and a "full" peripheral (max two tiles, 6-bit address, 64 bytes address space, 32-bit reads/writes, interrupt line).
27:08 Peripheral Bus Interface: The core-to-peripheral interface uses a data bus (similar to Wishbone); SPI is used within the templates for external testing.
35:08 Peripheral Capacity & IO: The system can accommodate up to 12 full and 16 byte peripherals, but overall size depends on design complexity. Outputs are multiplexed, allowing specific peripherals to drive pins.
41:19 Competition Success & Challenges: A goal of 20 entries is set. Challenges include managing large peripheral sizes (e.g., multiple VGA drivers) and the current exclusion of analog designs.
43:19 Community Engagement: Participants are encouraged to ask questions and coordinate designs in the Tiny Tape Out Discord competition channel.
47:11 Pre-Silicon Judging Proposed: Matt suggests judging designs based on their functionality on FPGA test boards (pre-silicon) to accelerate the competition loop. Mike uses an ECP5 FPGA board for testing.
50:27 Peripheral Design Ideas: Discussion includes using SPI for LCDs (as I2C is limited by bidirectional pins) and a WS2812 slave peripheral.
52:19 Verilog & System Verilog Support: Open-source tools support Verilog and System Verilog (with Yosys Slang plugin).
54:06 Fixed Clock Frequency: A suggested clock frequency for peripherals is 64 MHz, matching Tiny QV's operation.
56:44 Development Challenges: Mike notes the main challenge was building the robust infrastructure for integrating peripherals, which was validated through early tests.
58:12 Competition Judging Categories: Awards will be given for Best Documented, Best Tested, Best Demo Video, Most Unusual, and Community Favorite, with an independent judging panel.
59:31 FPGA Test Board Recommendations: For testing, Pico Ice is recommended for its integrated RP2040/ICE 40. Other options include Tang Nano and One Bit Squared Icebreaker.
1:00:51 Learning RISC-V CPU Design: Resources include Bruno Levi's course, Mike's Tiny QV core, Fazy RV, and Vex (in Spinal HDL).
1:02:24 Call to Action: Viewers are encouraged to template the Tiny QV repo, join the competition, and contribute to the open-source RISC-V ecosystem.