This video announces a new competition from the "open-source silicon stream" where the community is invited to build a crowdsourced RISC-V microcontroller. Hosted by Matt Van with special guest Mike Bell (creator of the TinyQV RISC-V core), the stream details a contest for participants to design and submit their own Verilog peripherals. These peripherals will be integrated with Mike's TinyQV core into a single, large, open-source System-on-Chip. The competition provides two peripheral templates—a simpler byte-based interface and a more advanced 32-bit interface with interrupt support—which allow for standalone testing before final integration. The final chip will be taped out on the Skywater 130nm process, with a submission deadline of around September 1st. The video also features news updates on recent open-source silicon events, new foundry support for Tiny Tape Out (including GlobalFoundries 180nm), and showcases new community tools like a 3D GDS viewer.
Building a Crowdsourced RISC-V Microcontroller: The TinyQV Peripheral Competition
00:00:05Introduction to the Stream: Host Matt Van introduces episode 17 of the open-source silicon stream, which focuses on community building and sharing the latest news in open-source ASIC design.
00:01:22Guest Introduction: Special guest Mike Bell (“Rebel Mike”) joins the stream. He is the creator of the TinyQV, a 4-bit serial RISC-V processor that was successfully taped out on Tiny Tape Out 6.
00:02:19News: Swiss Chips & IHP: Matt shares updates from the Swiss Chips conference, where a Tiny Tape Out workshop was held for 60 high schoolers using the IHP 130nm process.
00:05:31News: New Foundry Support: Tiny Tape Out is beginning work to support the GlobalFoundries 180nm process, with initial funding provided by Titus, the makers of the TKey open-source security key.
00:06:46News: 3D GDS Viewer: A new 3D GDS viewer created by Alexander Morvinc is showcased, allowing for interactive, 3D exploration of a chip design while it simulates.
00:14:29Competition Origin & Goal: Mike and Matt introduce a new competition for the community to design peripherals for the TinyQV microcontroller. The goal is to collaborate on a "crowdsourced open-source RISC-V microcontroller."
01:16:56Competition Timeline & Tape Out: The project will be taped out on the Skywater shuttle (closing around September 1st, 2024), giving participants approximately six weeks to create and submit their peripherals.
01:18:06Free Entry & Prizes: Entry is free, granting participants a tile on the chip. To receive a physical copy of the final microcontroller, a dev kit must be purchased. Prizes will be awarded for various categories like "Best Documented" and "Most Unusual."
01:19:28The Process: Participants will work from provided templates, create a Verilog-only peripheral, and submit it via a pull request. All accepted peripherals will be integrated into a single large RTL design.
01:24:13Peripheral Templates: Two templates are provided to simplify development:
Byte Peripheral: A simple, single-tile design with a 4-bit address (16 bytes of space) and an 8-bit data bus.
Full Peripheral: A more advanced, two-tile design with a 6-bit address (64 bytes of space), 32-bit data bus, and a dedicated interrupt line to the CPU.
01:25:21Standalone Testing: The templates include an SPI controller wrapper, allowing participants to fully test their peripheral using the standard Tiny Tape Out flow before it's integrated with the RISC-V core.
01:36:29IO Management: The final chip will feature an IO multiplexer, allowing the RISC-V core to programmatically route any of the chip's output pins to a specific peripheral.
01:48:11FPGA Validation: Submissions can be validated on FPGAs before tape-out. Mike has a custom ECP5-based test board, and an official Tiny Tape Out FPGA board is in development for those who want to test their designs.
01:54:06Design Clock Frequency: Participants should design and test their peripherals assuming a system clock frequency of 64 MHz.
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