This presentation provides a detailed technical overview of the STM32G4 microcontroller's High-Resolution Timer (HRTIM) peripheral. It is specifically designed for complex digital power conversion applications, such as switch-mode power supplies, where precise PWM waveform control is critical. The core of the HRTIM is a Delay-Locked Loop (DLL) which achieves resolutions down to 184 picoseconds, allowing for fine-grained adjustments to duty cycle, frequency, and phase. The presentation details the timer's architecture, which comprises a master timer and five synchronized timing units, a versatile crossbar for event routing, and extensive output management features like dead-time insertion and chopper modulation. Key functionalities covered include multiple counter modes (continuous, single-shot, up-down), advanced features like half-mode for resonant converters and auto-delayed mode for event-driven timing, and robust fault protection mechanisms. It also explains the timer's tight integration with other peripherals, detailing how it triggers ADCs for precise sampling, controls DACs for implementing slope compensation, and utilizes DMA for efficient, CPU-independent updates.
A Technical Overview of the STM32G4 High-Resolution Timer
00:00:02 - The Need for High Resolution: The STM32G4's High-Resolution Timer (HRTIM) is introduced as a solution for digital power applications like switch-mode power supplies. It offers significantly better duty cycle and frequency resolution than standard timers, which is crucial for precise voltage regulation and avoiding control loop instability.
00:01:14 - How High Resolution is Achieved: The timer's precision comes from a Delay-Locked Loop (DLL) that operates between 100-170 MHz. The DLL divides the timer's clock period into 32 fractional steps, achieving resolutions as fine as 184 picoseconds.
00:02:07 - System Architecture: The HRTIM is a complex peripheral consisting of a master timer and five identical, synchronizable 16-bit timing units (Timers A-E). It features a powerful crossbar unit to dynamically route events to its 12 outputs, along with built-in hardware for dead-time insertion, chopper modulation, burst mode control, and robust fault protection.
00:05:08 - Flexible Counter Modes: The timers support multiple operating modes: Continuous mode for fixed-frequency converters, and two single-shot modes (retriggerable and non-retriggerable) for generating precisely timed pulses triggered by external events.
00:08:36 - CPU Offloading Features: The HRTIM includes specialized modes to reduce CPU workload. Half Mode automatically maintains a 50% duty cycle when frequency is adjusted, ideal for resonant converters. Auto-Delayed Mode (00:09:46) allows output timings to be referenced from an external event with a programmable delay, useful for event-driven control schemes.
00:13:09 - Up-Down Counting for Symmetrical PWM: The timer supports up-down counting mode, which generates symmetrical, center-aligned PWM signals. This is beneficial for motor control and simplifies ADC sampling by providing a consistent, ideal trigger point at the peak of the waveform, regardless of the duty cycle.
00:15:26 - Hardware Dead-Time Insertion: To safely drive half-bridge power stages (e.g., in inverters), the HRTIM can automatically insert a programmable dead time between two complementary outputs. This prevents cross-conduction (shoot-through) and can be adjusted in real-time.
00:17:40 - Event and Fault Management: The system can dynamically respond to 10 configurable external events (e.g., from comparators or input pins) to implement features like cycle-by-cycle current control. It also includes an asynchronous fault management unit that can immediately place the outputs into a pre-defined safe state to protect the power hardware.
00:23:41 - Advanced Output Stage Features: The output stage includes a Chopper Unit to superimpose a high-frequency carrier signal, useful for driving isolated gate transformers. A hardware Burst Mode Controller (00:24:21) improves light-load efficiency by automatically skipping PWM pulses in a programmable pattern.
00:31:34 - Integrated Slope Compensation: The HRTIM provides dedicated triggers for the DAC to facilitate hardware-based slope compensation, a technique required to ensure stability in peak current mode converters. The timer automatically manages the generation of the necessary sawtooth waveform on the DAC output.
00:33:36 - Glitch-Free Parameter Updates: Critical registers are duplicated with shadow registers (preload mechanism). This allows for multiple configuration changes to be written on the fly, which are then applied simultaneously at a synchronized update event, preventing any intermediate glitches or malformed waveforms.
00:35:26 - DMA Integration for Complex Reconfiguration: The HRTIM can be dynamically reconfigured using DMA in a "burst mode." This allows a block of new settings to be transferred from memory to the timer's configuration registers without CPU intervention, enabling complex, on-the-fly changes to the timer's behavior.