This video provides a detailed technical overview of the STMicroelectronics (STM32) High-Resolution Timer (HRTIM) peripheral. The presentation outlines the timer's core architecture, which consists of a master timer and five independent yet synchronizable timing units (A-E), achieving a resolution as fine as 217 picoseconds. The session explores the HRTIM's extensive feature set, including its versatile crossbar for event management, multiple counter operating modes, and specialized functions like Push-Pull, Half Mode, and Auto-Delayed Mode, which are designed to simplify complex power conversion and motor control applications. Key functionalities such as programmable dead-time insertion, a chopper unit for transformer-coupled gate driving, and a Burst Mode controller for light-load efficiency are explained. The presentation places a strong emphasis on the timer's robust fault management system, which uses five dedicated inputs and system-level error detection to asynchronously force outputs into a safe state. Finally, it covers the HRTIM's tight integration with other peripherals, including direct hardware triggers for ADCs and DACs, numerous interrupt and DMA sources, and a practical application example of a triple-interleaved converter.
A Deep Dive into the STM32 High-Resolution Timer (HRTIM)
0:01:40 - High-Resolution Capabilities: The HRTIM is an advanced timer with a resolution of 217 picoseconds, achieved with a 480 MHz input clock. It is designed for generating complex, high-frequency PWM signals for applications like digital power supplies (SMPS), solar converters, and motor control.
0:02:58 - Core Architecture: The HRTIM is not a single timer but a system of six 16-bit counters: one Master Timer and five individual Timing Units (A-E). A large central crossbar allows events from any timer or external source to control the outputs, offering immense flexibility.
0:06:58 - Counter Operating Modes: The counters support three primary modes: Continuous (for fixed-frequency PWMs), Single Shot (for generating a single pulse), and Retriggerable (a single-shot mode where the pulse can be extended by new triggers).
0:09:11 - Set/Reset Crossbar: Each output's waveform is defined by programming set and reset events into a crossbar. This allows for waveforms with multiple pulses per period, built from a combination of up to 32 different event sources. Shadow registers ensure glitch-free updates on the fly.
0:11:20 - Half Mode Operation: A dedicated hardware feature that simplifies the creation of variable-frequency, 50% duty cycle waveforms, common in resonant converters. When the period register is updated, the compare register is automatically set to half the period, offloading the CPU.
0:13:19 - Auto-Delayed Mode: This mode allows an output event to be triggered a specific delay after an external event occurs. The timer captures the arrival time of the external signal and computes the new compare value on the fly, which is ideal for precise, reactive timing.
0:14:56 - Push-Pull Mode: This feature simplifies the control of push-pull and resonant converters by automatically generating two out-of-phase output signals from a single compare value, reducing the number of resources and CPU overhead required.
0:17:39 - Dead-Time Insertion: To prevent shoot-through in half-bridge power stages, the HRTIM can automatically insert a programmable dead time between two complementary outputs. The rising and falling edge dead times can be adjusted independently.
0:18:56 - Master Timer for Synchronization: The Master Timer's primary function is to synchronize the five individual timing units. Its events (e.g., period match) can be used to reset the other timers, which is essential for managing multi-phase converters.
0:22:18 - Advanced Event Filtering: To ensure reliable operation in noisy environments, external events can be managed with sophisticated hardware filters, including "Blanking" (ignoring events during a specific window) and "Windowing" (accepting events only within a specific window).
0:26:54 - Burst Mode & Chopper Unit: The timer includes a hardware Burst Mode controller to improve light-load efficiency by skipping pulses. A Chopper unit can superimpose a high-frequency carrier signal onto the PWM output, which is useful for driving isolated gate drivers.
0:28:34 - Robust Fault Management: A critical safety feature, the HRTIM has five dedicated fault inputs that can asynchronously shut down PWM outputs to a pre-defined safe state. It can also react to system-level errors like clock failure or a core lockup.
0:31:42 - Peripheral Triggering: The HRTIM is tightly integrated with other peripherals. It can generate up to four independent ADC triggers at precise points in the PWM cycle for synchronized measurements and can also trigger DAC updates for setting comparator thresholds in real-time.
0:36:38 - Application Example: The video demonstrates a practical use case: a triple-interleaved converter. The Master Timer synchronizes three timing units (A, B, C) with a 120-degree phase shift, showcasing how the architecture simplifies complex multi-phase power supply designs.