This live stream documents the process of creating a quadrature encoder peripheral for the open-source Tiny Tapeout RISC-V competition. Before the main technical session, the host shares an update on open-source silicon news, including a detailed look at his recent visit to the IHP semiconductor labs. This segment features photos and explanations of advanced fabrication and testing equipment, such as a Secondary Ion Mass Spectrometry (SIMS) machine for elemental analysis and a fully automated wafer prober for post-fabrication testing. The core of the stream is a live coding session where the host adapts an existing Verilog project for a quadrature encoder. He demonstrates its functionality on an FPGA, explaining the need for signal debouncing, and then integrates the logic into the competition's RISC-V peripheral template. The process involves wrapping the encoder module, connecting it to the processor's bus, and using GitHub Actions for automated verification and layout generation. The stream concludes with the peripheral's design successfully passing the initial layout generation, with the host outlining future work before final submission.
From News to Hardware: Building a RISC-V Peripheral
0:03 The stream's primary goal is introduced: to build a quadrature encoder peripheral and submit it to the new Tiny Tapeout RISC-V competition, which aims to create a crowdsourced, open-source microcontroller.
3:03 The host shares insights and photos from a recent visit to the IHP semiconductor factory, a partner for open-source chip manufacturing.
4:50 He details a Secondary Ion Mass Spectrometry (SIMS) machine, explaining how it analyzes a wafer's elemental composition layer-by-layer to verify the manufacturing process, such as the diffusion of a transistor's N and P regions.
8:13 The stream showcases an automated wafer testing system. It uses a sophisticated probe card with hundreds of microscopic pins to make contact with chip pads, allowing for comprehensive JTAG testing across different temperature ranges before the wafer is diced.
17:51 The RISC-V peripheral design competition is highlighted as a free way for enthusiasts to get their custom peripheral designs fabricated on silicon as part of a larger collaborative project.
19:42 The host outlines his specific project: adapting the quadrature encoder logic from his "Zero to ASIC" course to create a peripheral. His long-term plan is to use this peripheral with another community member's LED driver peripheral to recreate his RGB mixer project, all controlled by the RISC-V core.
24:24 A live demo on an FPGA shows the functionality of the quadrature encoder, including the raw A/B signals, the effect of noise, the clean debounced output, and the final PWM signal being controlled by turning the encoder knob.
32:35 The host begins the live coding session, starting from the competition's Verilog template for a simple byte-addressable peripheral provided by community member Mike Bell.
38:10 He integrates his existing Verilog modules (a strobe generator, debouncer, and encoder) into the template, connecting the encoder's inputs to the peripheral's pins and its output count to a register that the CPU can read.
45:38 The completed Verilog code is pushed to GitHub, triggering the Tiny Tapeout GitHub Actions workflow, which automatically runs synthesis and place-and-route to generate a GDS layout file.
51:55 The automated workflow successfully generates the physical layout (GDS file) for the peripheral, confirming the design is valid for fabrication. As expected, the test and documentation steps fail because they have not yet been implemented.
58:39 The host concludes by creating a to-do list for the project, which includes writing tests, adding support for more encoders, and making the debounce rate configurable before officially submitting it as a pull request to the competition.