This lecture by Professor Chris Mack, part of the "Chemical Processes for Micro- and Nanofabrication" course, explains the copper dual damascene process used in modern semiconductor manufacturing. The video begins by outlining the motivation for the industry's switch from aluminum to copper for interconnects—namely, copper's lower resistivity, which enables faster chip performance. However, this switch introduced two significant challenges: copper is a fast-diffusing contaminant that can destroy silicon transistors, and it is extremely difficult to pattern using traditional subtractive plasma etching.
The lecture details the solutions to these problems. To prevent contamination, barrier layers (like TiN or Ta) and tungsten plugs are used to isolate the copper from the silicon. To overcome the etching issue, an additive manufacturing technique known as the "damascene process" is employed. The video provides a step-by-step breakdown of the "via-first" dual damascene method, where trenches for wires and vias for vertical connections are etched into a dielectric material first. These structures are then filled simultaneously in a single copper deposition step, which involves electroplating onto a thin seed layer. The process is completed with chemical-mechanical planarization (CMP) to create a flat, finished layer, a technique that is repeated to build the complex multi-level wiring of a modern chip.
The Copper Dual Damascene Process in Chip Manufacturing
0:21 - The Switch to Copper: The semiconductor industry transitioned from aluminum to copper for chip interconnects because copper has significantly lower electrical resistivity. This results in a lower RC time constant, allowing for faster signal propagation and reduced power consumption.
1:14 - The Two Main Problems with Copper: Despite its advantages, using copper presents two major challenges in fabrication.
Contamination: Copper is a "deep level defect" in silicon, meaning it diffuses quickly and can severely damage or destroy transistor performance.
Etching: Copper cannot be easily patterned with standard plasma etching because its reaction byproducts are not volatile, making traditional "subtractive" methods unfeasible.
1:52 - Solving the Contamination Issue: To prevent copper from reaching the silicon, a barrier layer (such as Titanium Nitride or Tantalum) is deposited over the entire wafer. Tungsten is used as the first metal to make direct contact with the silicon source and drain.
3:50 - The Additive Solution: The Damascene Process: To pattern copper without etching it, an "additive" technique called the damascene process is used. Named after a decorative metal inlay art form from Damascus, this process involves etching a pattern into a dielectric material first and then filling that pattern with copper.
8:05 - The Dual Damascene Process: This is an efficient method for creating both the horizontal wires (trenches) and the vertical connections between layers (vias) at the same time.
In the "via-first" method, a hole for the via is etched, followed by the wider trench pattern above it.
This creates a combined structure that is filled with copper in a single step, which is why the process is called "dual."
10:43 - The Copper Deposition Method: Filling the high-aspect-ratio trenches and vias is a multi-step process.
First, a thin barrier layer is deposited to line the structure.
Next, a very thin copper "seed layer" is sputtered onto the barrier.
Finally, the structure is filled completely using copper electroplating, which offers superior gap-fill capability compared to sputtering.
11:21 - Planarization and Completion: After the copper fill, Chemical-Mechanical Planarization (CMP) is used to polish the wafer. This removes the excess copper from the surface, leaving it only inside the patterned trenches and vias, and creates a perfectly flat layer ready for the next level of interconnects.
14:57 - Multi-Level Interconnects: Modern chips use many layers of copper built using this process. The wires in the lower layers are thin for short, local connections, while the wires in the upper layers are made thicker and wider to serve as low-resistance "global" interconnects for long-distance signals.