This video introduces and demonstrates the Etherdecode, a custom-designed hardware adapter for triggering on and decoding 100M Ethernet traffic using standard oscilloscopes and logic analyzers. The device functions as a passive tap with dual RJ45 ports, built around a Microchip LAN8720A Ethernet PHY and an FPGA. It outputs an 8-bit parallel data stream and provides several intelligent features, including a dedicated trigger output, a byte-count mode for easy packet navigation, and a marker output that can highlight specific fields within an Ethernet frame, such as MAC/IP addresses and port numbers. The creator discusses the design choices, potential use cases for low-level hardware debugging where software tools fall short, and future possibilities, including a potential gigabit version and the possibility of open-sourcing the design if it does not prove popular.
Decoding Ethernet at the Hardware Level: The Etherdecode Adapter
0:00 Product Introduction: The video presents a new board, the Etherdecode, designed to help oscilloscopes and logic analyzers trigger on and decode 100M Ethernet traffic at the physical layer.
0:17 Core Functionality: It acts as a passive pass-through tap with dual RJ45 ports. A switch allows the user to monitor either the transmit or receive pair, and a second switch enables link establishment when connected to a single device or a switch's mirror port.
1:25 Key Components: The design is based on a Microchip LAN8720A PHY and an FPGA. A crucial feature is the switch-selectable onboard termination, which can be disabled to minimize loading on the line when tapping.
2:35 Onboard Indicators: The board includes several LEDs for status indication: power, link status, an "Error" light for marginal signal conditions, and a custom "Packet" LED that provides a more accurate indication of packet reception than the PHY's standard activity LED.
3:29 Data Output: The device outputs an 8-bit parallel data stream via a 20-way header, along with ground pins and a marker output, designed for easy connection to logic analyzer probes.
4:25 Intelligent Trigger and Marker: The board generates a clean trigger pulse at the start of every packet. It also features a marker output with two modes: a simple pulse-per-byte clock or a mode that highlights specific fields in the packet (destination/source MAC, EtherType, IP addresses, ports).
6:34 Byte-Count Mode: A key debugging feature is a mode that replaces the data output with a simple byte counter (0, 1, 2, 3...). This allows a user to easily navigate to a specific byte offset within a long packet before switching back to view the actual data at that location.
7:46 Business Plan & Future Development: The creator has set up a website (etherdecode.com) to sell the initial batch. Future plans depend on its popularity and may include a version with a case or open-sourcing the design.
8:07 Gigabit Version Considered: A potential future version could support Gigabit Ethernet, though this presents challenges with the 125 MHz data rate, likely requiring an onboard FIFO buffer to output data at a slower speed for standard oscilloscopes.
Summary of YouTube Comments:
The comments are overwhelmingly positive, with many viewers praising the device as a clever and useful tool for low-level debugging. Several commenters identify specific, advanced use cases where traditional software sniffers would be insufficient, including reverse-engineering custom protocols, timing attack analysis, Tempest emanation testing, and debugging time-sensitive Ethernet standards like IEEE1588. There are numerous suggestions for future product development, such as an affordable USB3 sniffer, a Wi-Fi (802.11) version, and strong interest in the proposed Gigabit model. The "byte-count" mode is frequently singled out as a particularly smart feature. Overall, the community expresses strong appreciation for the creator's expertise and the practical, real-world utility of the product.