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Abstract:
This video details the creation of a low-cost, custom hardware tool for real-time decoding and analysis of 100BASE-T Ethernet traffic on a standard mixed-signal oscilloscope. The project was motivated by the need to debug the low-level timing and performance of a custom Ethernet-based data distribution board, a task for which software tools like Wireshark are insufficient and dedicated scope features are expensive. The solution involves tapping an Ethernet line with a standalone PHY (Physical Layer) chip, which converts the line signal into a digital RMII (Reduced Media-Independent Interface) format. This digital data is then fed into a small FPGA programmed with simple VHDL to detect the start of a packet, deserialize the data, and output it as an 8-bit parallel bus. This allows the oscilloscope to trigger on and display the contents of Ethernet packets byte-by-byte, enabling precise correlation between network traffic and other hardware signals. The creator demonstrates the entire process, from the initial problem to the final prototype, and discusses its potential use cases for developers and reverse engineers.
Cheap Ethernet Decoding: A DIY Hardware Solution
0:00 - The Initial Problem: The video starts by explaining the limitations of an older RS-485 based data distribution system, which prompted a move to a more scalable Ethernet-based solution for large-scale lighting installations.
2:20 - A New Ethernet Board: A custom board using a PIC32 microcontroller and a Wiznet W5500 Ethernet chip is introduced. While functional, debugging its real-time performance and buffer management proved difficult.
4:07 - On-Board Diagnostics: The new board features a small OLED display and touch buttons for on-site configuration and displaying real-time statistics like packet counts and run times, which aids in initial debugging.
7:32 - The Core Debugging Challenge: The main issue is the inability to see the precise timing of incoming Ethernet packets. Software tools can't be easily synchronized with hardware signals, and the physical Ethernet signal is too complex to interpret visually on a scope.
11:51 - The First Step to a Solution: The creator uses a standalone Ethernet PHY (Physical Layer) chip to tap the Ethernet line. The PHY's "data valid" output provides a clean digital signal on the oscilloscope, showing exactly when a packet starts and ends.
15:53 - Understanding the RMII Interface: The PHY chip outputs data using the RMII standard, which provides a 50 MHz clock, a "data valid" signal, and two data lines (RXD0, RXD1), carrying two bits of data per clock cycle.
17:25 - The Synchronization "Trick": A key realization is that the Ethernet Start Frame Delimiter (SFD) creates a unique signature where the "data valid" and both data lines go high simultaneously. This provides a simple, reliable hardware trigger to know exactly when to start parsing the data stream.
21:47 - FPGA for Decoding: A small Lattice FPGA is used to process the RMII signals. With just a few lines of VHDL, the FPGA waits for the SFD sync signal, shifts the incoming data into an 8-bit register, and outputs a clean parallel byte stream for the duration of the packet.
23:48 - Real-Time Scope Decoding: The FPGA's parallel output is fed into the oscilloscope's logic analyzer inputs. This allows the scope to display the packet's data content (MAC addresses, UDP payload, etc.) as a decoded bus, synchronized with the packet's arrival.
26:21 - Advanced Triggering: Using the scope's edge burst triggering feature on a "per-byte" pulse from the FPGA, it's possible to trigger on a specific byte within the packet (e.g., the 10th byte), which is useful for targeted debugging.
27:09 - Prototype and Potential Product: The creator presents a compact PCB prototype that integrates the PHY, FPGA, and connectors. He concludes by asking for feedback on the tool's usefulness, considering its applications in embedded development, reverse engineering, and performance analysis.
Summary of YouTube Comments
The user comments reflect a highly positive and engaged reception from a technically knowledgeable audience. The key themes are:
Overwhelmingly Positive Reception and Commercial Interest: The most common sentiment is praise for the cleverness and utility of the project. Many users express a strong desire to purchase the tool, stating they would order one or more immediately if it were made available as a product.
Technical Suggestions and Alternatives: Several experienced viewers offer valuable technical feedback, with the most frequent suggestion being to use the MII (Media-Independent Interface) instead of RMII. They note that MII, while using more pins, provides a recovered clock that is locked to the incoming data, which would reduce the jitter and latency inherent in the RMII approach. Other suggestions include using different PHYs or tapping methods.
Real-World Use Cases and Validation: Developers working with embedded systems (PIC, ARM Cortex) and FPGAs confirm the tool's usefulness. They highlight the difficulty of correlating low-level hardware events with network traffic using software like Wireshark alone and see the device as a perfect solution for that specific problem.
Appreciation for Content Quality: Many comments praise the high-quality, in-depth technical content of the channel. Several users note that they were so impressed they subscribed immediately after discovering the video.
Presentation Feedback: A minority of comments mention that the creator's fast speaking pace can be difficult to understand. There are also a few helpful suggestions related to the UI of the original project board, such as how to prevent OLED screen burn-in.