Here is the abstract and summary for the provided transcript:
Abstract:
This video provides an in-depth exploration of Power Distribution Networks (PDNs) in Printed Circuit Board (PCB) design, emphasizing their measurement, modeling, and practical implications. The presenter characterizes a custom-designed PDN test board, measuring its impedance profile across various frequencies using a vector network analyzer (BOD 100) and an oscilloscope-based bodplot. The impact of regulators, bulk capacitors, and decoupling capacitors on the PDN's impedance is demonstrated by observing changes when components are removed. Furthermore, a real-time, time-domain experiment illustrates how PDN impedance translates into voltage noise at the point of load when subjected to dynamic current demands. Finally, the video compares real-world measurements with a simplified LTSpice simulation, showcasing how basic models can accurately approximate complex PDN behavior.
Exploring Power Distribution Networks (PDNs) on PCBs
0:00 Introduction to PDNs: The video introduces the fundamentals of power distribution networks (PDNs) on PCBs, their impedance profile versus frequency, and the importance of understanding how capacitors, regulators, and loads affect system performance.
0:54 Sponsored by JLCPCB: The video highlights JLCPCB's affordable and reliable PCB manufacturing and assembly services, including advanced multi-layer options and easy order processes.
2:00 Simplified PDN Model: A typical PCB power structure is simplified, showing components like a power source, linear regulator (LDO), input/output capacitors, traces with inherent resistance and inductance, bulk/local decoupling capacitors, and the integrated circuit (IC) load.
4:48 Importance of Impedance: The video explains that the IC power pin "sees" a frequency-dependent impedance looking back at the power source. A low and flat impedance profile is crucial for stable voltage, preventing brownouts, and mitigating EMI/signal integrity issues.
8:02 Components Dominating Impedance: Different components dominate the PDN's impedance at various frequency bands:
Low Frequencies (up to 10-20 kHz): Voltage Regulator Module (VRM) or Power Management IC (PMIC).
Mid Frequencies (10 kHz to 1 MHz): Bulk capacitors.
Higher Frequencies: Smaller decoupling capacitors (MLCCs) due to lower ESL and ESR.
Very High Frequencies: On-die capacitance of ICs and eventually the inductive region where inductance dominates.
10:30 PDN Test Board Design: A custom-designed PDN test board is used for easy, controlled experimentation. It features exchangeable elements, known trace dimensions, and accessible test points for two-port shunt-through impedance measurements.
13:11 Two-Port Shunt Through Measurement: The video assumes prior knowledge of this measurement method and details the calibration process using a similar fixture for accuracy.
16:16 BOD 100 Measurements (Unpowered vs. Powered):
Unpowered: The PDN exhibits a capacitive impedance profile, trending downwards with increasing frequency, dominated by decoupling capacitors.
Powered: The active regulator significantly lowers the low-frequency impedance. At higher frequencies, impedance is slightly higher than unpowered due to capacitor derating from DC bias.
Removing one bulk decoupling capacitor (C6) increases impedance in the 10-100 kHz range.
Removing the second bulk capacitor causes impedance to peak over 1 Ohm at 20-25 kHz.
Removing the point-of-load decoupling capacitor (C7) eliminates the low-impedance path at high frequencies, leading to an immediate inductive region and a much worse overall impedance profile.
25:05 Time Domain Demonstration (Oscilloscope): A practical setup shows the real-time effect of PDN impedance on voltage noise. A switchable current sink (MOSFET load) driven by a signal generator perturbs the PDN, and an oscilloscope monitors the resulting voltage ripple.
32:56 Frequency-Dependent Noise: The voltage noise is shown to correlate directly with the PDN's impedance profile:
100 Hz: Low noise (~27mV peak-to-peak).
1 kHz: Increased noise (~108mV peak-to-peak).
10 kHz: Even higher noise (corresponding to the impedance peak).
100 kHz: Noise reduces as impedance drops again.
Square Wave: Produces different noise characteristics due to its harmonic content, demonstrating superposition of impedances.
35:48 Automated Measurement (Bodplot): The oscilloscope's built-in bodplot feature can automate frequency sweeps, replicating the VNA's impedance profile measurements using a current load stimulus.
38:07 LTSpice Simulation: A simplified LTSpice model of the PDN, built from component datasheets (e.g., capacitor ESL/ESR) and PCB trace properties (resistance, inductance from Altium Designer), accurately approximates the measured impedance profile.
43:07 Conclusion: The video concludes by reiterating the importance of understanding, measuring, and simulating PDNs for robust PCB hardware design, providing insights into various methods and their practical implications.