This video provides a comprehensive exploration of Power Distribution Networks (PDNs) in real-world PCB hardware design. It covers characterizing, measuring, and modeling PDN impedance profiles, demonstrating their critical impact on system performance. The presenter uses a custom-designed test board to illustrate how various components like voltage regulators, bulk capacitors, ceramic capacitors, and PCB traces influence the impedance across different frequency bands. Measurement techniques, including a BOD 100 vector network analyzer for impedance vs. frequency plots and an oscilloscope with a switched current load for time-domain voltage noise analysis, are detailed. The video also shows how to model PDNs using LTSpice, comparing simulated results with actual measurements. Key takeaways emphasize the importance of achieving a low and flat impedance profile to prevent issues such as voltage drops, brownouts, EMI, and signal integrity problems. The video is sponsored by JLCPCB for PCB manufacturing and assembly.
Understanding Power Distribution Networks in PCB Design
0:00 Introduction to PDNs: The video introduces the concept of Power Distribution Networks (PDNs) in PCBs, emphasizing the importance of characterizing and measuring their impedance profiles to understand their impact on hardware design.
0:46 JLCPCB Sponsorship: The video highlights JLCPCB for sponsoring the project by manufacturing and assembling the custom PDN test PCBs, noting their affordability and ease of use for multi-layer boards.
2:01 Simplified PDN Model: A simplified circuit model of a typical power structure on a PCB is presented, detailing components like regulators, input/output capacitors, and power traces with their non-ideal resistance and inductance.
4:48 Importance of Low Impedance: The presenter explains that an IC's power pin must maintain stable voltage, not just at DC but also at AC, making a low and flat PDN impedance profile crucial to prevent voltage drops, brownouts, EMI, and signal integrity issues, especially during high-current transients.
8:04 Components Shaping Impedance Profile: The video illustrates how different components dominate the PDN impedance profile at various frequency bands: voltage regulators (VRM) at low frequencies (up to ~10-20 kHz), bulk capacitors (10 kHz - 1 MHz), smaller ceramic capacitors (higher frequencies), and ultimately on-die capacitance and trace inductance.
10:31 The PDN2 Port Test Board: The presenter introduces a custom-designed PDN test board, built for easy testing and demonstrating the effects of various capacitors, regulators, series elements, and loads on the impedance profile.
13:11 Two-Port Shunt-Through Measurement: The video details the measurement setup using a BOD 100 vector network analyzer configured for a two-port shunt-through impedance measurement, including calibration procedures with custom fixtures.
17:17 Unpowered vs. Powered Impedance: Measurements compare the PDN impedance profile of the board when unpowered versus powered, showing that the active regulator significantly lowers low-frequency impedance and how capacitor derating slightly increases impedance at higher frequencies when powered.
20:20 Interpreting the Impedance Curve: The measured impedance profile reveals distinct regions: the low-frequency LDO-dominated region (e.g., ~26 milliohms at 100 Hz, peaking at ~300 milliohms at 10 kHz), followed by regions where bulk and ceramic capacitors reduce impedance, until series inductance dominates.
22:24 Impact of Component Removal: The video demonstrates the critical role of capacitors by showing how removing bulk decoupling capacitors and the point-of-load ceramic capacitor drastically increases impedance, especially at their respective dominant frequencies, resulting in a much worse impedance profile.
25:01 Time Domain Demonstration: A practical setup using a switched current load (MOSFET with resistors) driven by a signal generator is used to observe the real-world voltage noise (dips and overshoots) at the PDN output on an oscilloscope.
30:51 Frequency-Dependent Voltage Noise: Real-time oscilloscope traces demonstrate that voltage noise (ripple) at the output varies significantly with the load current's switching frequency, directly correlating with the measured PDN impedance profile. Higher impedance at a given frequency leads to greater voltage noise.
35:46 Automated Bode Plot Measurement: The oscilloscope's built-in Bode plot feature is used to automate the voltage noise measurement across frequencies, confirming that its shape closely matches the impedance profile obtained from the vector network analyzer.
38:26 LTSpice Simulation: The video shows how to model the PDN in LTSpice, extracting component parameters (e.g., trace resistance/inductance from PCB design software, capacitor ESL/ESR from datasheets) to simulate the impedance profile.
41:51 Simulation vs. Measurement Comparison: The LTSpice simulation results are compared to the real-world measurements, demonstrating a good fit in the overall shape and trends of the impedance profiles, validating that even simple models can approximate complex PDNs.
43:08 Conclusion: The video concludes by reiterating the importance of PDN analysis for real-world PCB design, the impact of impedance on voltage noise, and the utility of both measurement and simulation techniques.