This video provides a comprehensive exploration of Power Distribution Networks (PDNs) in Printed Circuit Boards (PCBs), focusing on their characterization, measurement, and modeling. The presenter demonstrates how to measure the impedance profile versus frequency using a custom-designed test board and a BOD 100 vector network analyzer, highlighting the distinct contributions of various components like voltage regulators (VRMs), bulk capacitors, and multi-layer ceramic capacitors across different frequency bands. Furthermore, the video illustrates the real-world impact of PDN impedance on voltage noise and ripple at the point of load in the time domain, utilizing an oscilloscope and a switchable current sink. Finally, it demonstrates how to accurately model these complex PDN behaviors using LTSpice, comparing simulated results against measured data to validate the importance of PDN design in hardware performance and signal integrity.
Summarizing Power Distribution Networks: Measurement and Modeling
0:00 Introduction to PDNs: The video aims to expose viewers to the basics of Power Distribution Networks (PDNs) in real-world PCBs, focusing on characterizing and modeling their impedance profile versus frequency. This is crucial for understanding how capacitors, regulators, and loads affect system performance.
0:54 PCB Manufacturing Sponsor: The custom PDN test PCBs used in the video were manufactured and assembled by JLCPCB, highlighting their affordability and capabilities, including up to 32 layers and advanced finishes.
2:31 Simplified PDN Model: A typical PDN involves a power source, a regulator (e.g., LDO) with input/output capacitors, power traces (with non-ideal resistance and inductance), bulk decoupling capacitors, local decoupling capacitors (e.g., 100nF near ICs), and the integrated circuit (IC) load.
3:54 Importance of PDN Impedance: The goal of PDN design is to ensure stable voltage at the IC power pins, even during transient current demands. A simplified view shows the IC looking back at a frequency-dependent impedance. High impedance at certain frequencies can lead to voltage drops, brownouts, EMI, and signal integrity issues. The ideal is a low and flat impedance profile, often defined by a "target impedance."
8:14 Factors Influencing Impedance Profile: Different components dominate the PDN impedance profile at different frequency bands:
Low Frequencies (up to ~10-20 kHz): Voltage Regulator Module (VRM) or Power Management IC (PMIC) control loops.
Higher Frequencies (1 MHz - On-Die): Smaller, lower Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR) multi-layer ceramic capacitors, followed by on-die capacitance.
Very High Frequencies: Inductive region where ESL dominates. Resonances (peaks and troughs) are common due to component interactions.
10:31 Custom PDN Test Board: A "PDN2 port test board" was designed for easy testing, allowing exchange of bulk capacitors, regulators, filters, and loads to observe their effect on the impedance profile. It includes specific measurement points for a two-port shunt through method.
13:09 Two-Port Shunt Through Measurement: The video details the measurement setup using a BOD 100 vector network analyzer, emphasizing the need for calibration (open, short, load) with fixtures matching the point of load for accuracy.
17:17 Measurement Results - Unpowered vs. Powered:
Unpowered: Shows a capacitive impedance profile initially, then self-resonant points, and finally an inductive region.
Powered: The regulator's active control loop significantly lowers the impedance at low frequencies. Capacitor derating (capacitance drop due to DC bias) causes a slightly higher impedance in the higher frequency range compared to the unpowered state.
22:24 Impact of Removing Capacitors: Removing bulk decoupling capacitors (C5, C6) leads to a much higher impedance, especially in the 10-100 kHz range, demonstrating their critical role. Removing the point-of-load multi-layer ceramic capacitor (C7) eliminates the low impedance path at higher frequencies, drastically worsening the impedance profile and showing immediate transition to an inductive region.
25:00 Time Domain Demonstration with Oscilloscope: A practical demonstration illustrates voltage noise at the point of load using a switchable current sink (MOSFET with load resistors) driven by a signal generator.
27:01 Voltage Dip and Overshoot: When current demand increases (FET turns on), the voltage rail dips; when demand decreases (FET turns off), it overshoots, due to the series impedance of the PDN.
32:11 Frequency-Dependent Noise: The measured RMS and peak-to-peak noise significantly increase at 1 kHz and especially 10 kHz, correlating directly with the impedance peaks observed in the frequency domain measurements. Noise reduces again at 100 kHz as impedance drops.
34:17 Square Wave Effect: Using a square wave (superposition of sine waves) causes a different noise profile due to the addition of impedances at various harmonic frequencies, demonstrating complex ringing in an underdamped system.
35:50 Automated Bode Plot Measurement: The oscilloscope's built-in Bode plot feature can automate the process, confirming the same curve shape as the VNA, measuring the V/I transfer function (impedance) by applying a current stimulus and monitoring the voltage.
38:03 LTSpice Simulation: A simplified LTSpice model is created to capture the PDN, using LDO models, traces modeled as series R and L (extracted from PCB design software), and capacitors modeled with ESL and ESR (from manufacturer data, including derating).
41:51 Simulation vs. Measurement Comparison: The simulation's impedance profile closely matches the real-world measurements, validating that even simple models can approximate complex PDN behavior.
42:51 Conclusion: The video effectively demonstrates various methods for measuring and simulating PDNs, highlighting the critical impact of PDN impedance characteristics on voltage noise and overall system performance in real-world PCB hardware design.