0:00:02 Introduction: This episode discusses the Sky 130 ROM compiler, focusing on testing and characterization rather than design.
0:00:18 Tiny Tapeout 09: Two test ROMs were taped out on Tiny Tapeout 09 to compare performance and leakage current of different transistor types.
0:01:04 AT2600 Project: The AT2600 project by renaldas also utilizes the ROM compiler for storing four built-in 32-kilobit ROM cartridges.
0:01:51 Layout Inspection: The layout of the AT2600 project and the test ROMs can be inspected using KLayout by downloading the Oasis file from the GitHub repository.
0:03:07 Test ROM Details: The test ROMs include one 32-kilobit ROM and two 4-kilobit ROMs with different aspect ratios.
0:03:50 Automated Generation: The core of the ROM macro, including the bit array, muxing, word line drivers, and address decoding, is automatically generated.
0:05:35 Manual Work: Some aspects, like power rail connections, address decoder connections, and final output driver integration, are still done manually.
0:07:08 Digital Block: A digital block using standard cells sends test signals to the ROMs for characterization.
0:07:55 Testing Methodology: The digital block uses registers and a mux to send precise address sequences and capture the ROM's output, measuring hold time and setup time.
0:10:15 Calibration: Pass-through signals are used to calibrate out mux delays and routing variations.
0:12:26 Future Chip: The chip is expected to return in mid-2025, which will allow for correlation between measurements and simulations.
0:12:28 Digital Block Design: The digital block is designed with a focus on neatness and matching, using a programmatic approach to control cell placement and routing.
0:13:36 Programmatic Layout: A Python-based tool called "gen_control" is used to generate the digital block layout programmatically, creating a TCL script executed by Magic.
0:18:41 Conclusion: The main goal of this test is to validate the ROM's performance and correlate measurements with simulation and modeling results.
0:18:57 Modeling: Accurate modeling of the ROM is crucial for estimating delay without full post-layout simulations.