Abstract:

This video introduces a revolutionary capacitor-less DRAM architecture, dubbed 2T0C (two transistors, zero capacitors), developed by IMC to address the increasing scaling challenges of traditional DRAM. The innovation centers on using Indium Gallium Zinc Oxide (IGZO) for one of the transistors, which significantly reduces leakage and allows data to be retained for hours without refresh, drastically cutting power consumption. Fabricated using low-temperature, industry-compatible thin-film processes on 300mm wafers, this technology not only offers comparable endurance and speed to current DRAM but also opens up unprecedented possibilities for vertical stacking directly onto processor cores or in high-density memory arrays. Despite facing challenges related to widespread manufacturing adoption and market timing, IMC's 2T0C DRAM presents a compelling vision for a more dense, power-efficient, and integrated memory future, particularly for demanding applications like AI accelerators.

Summarizing IMC's Capacitor-less DRAM: A New Era for Memory

• 0:00:02 The DRAM Scaling Problem: Traditional DRAM relies on a transistor and a capacitor, but scaling the capacitor has become a bottleneck, consuming too much space and power, limiting memory density.
• 0:00:32 IMC's Solution: 2T0C DRAM: IMC proposes a new DRAM architecture that eliminates the capacitor entirely, using a "two transistor, zero capacitor" (2T0C) cell. This design enables longer data retention, similar endurance to modern DRAM, and lower manufacturing temperatures.
• 0:01:16 Challenges of Traditional 1T1C DRAM: Explains that conventional DRAM requires refreshing data every few milliseconds due to charge leakage from the capacitor, which consumes significant power and takes up more physical space than the transistor.
• 0:02:50 How the 2T0C Cell Works: The 2T0C cell stores charge in the parasitic capacitance of one of its transistors. The key is using Indium Gallium Zinc Oxide (IGZO) for the channel of the storage transistor.
• 0:03:30 The Role of IGZO: IGZO offers extremely low leakage when turned off, allowing the charge to be held for much longer than in standard silicon transistors. This material is integrated using thin-film deposition techniques during manufacturing.
• 0:04:30 Early Success (2020): IMC successfully built working 2T0C cells on 300mm wafers with 45nm gate lengths, demonstrating data retention for over 400 seconds without refresh, significantly outperforming conventional DRAM's 64-millisecond refresh cycle.
• 0:05:48 Key Improvements by 2021:
  • Retention: Increased to over 1,000 seconds (nearly triple the initial result).
  • Endurance: Achieved over 10^11 write and read cycles, meeting real-world DRAM requirements.
  • Speed: Read and write times dropped below 10 nanoseconds, making it viable for high-performance memory systems.
• 0:06:26 Manufacturing Advancements: IMC fabricated these cells on 300mm wafers using industry-friendly processes, scaling gate lengths from 45nm down to 14nm (comparable to commercial DRAM) and exploring thinner IGZO layers (down to 5nm).
• 0:07:12 Extended Retention to 4.5+ Hours: Further process refinements, such as replacing ion beam etching with reactive ion etching, eliminated leakage paths and extended data retention beyond 4.5 hours.
• 0:07:49 Roadmap Candidate Status: The research has progressed from proving a concept to building a potentially manufacturable technology, though challenges remain.
• 0:07:49 Remaining Challenges:
  • IGZO Qualification: IGZO is not yet widely used in mainstream semiconductor manufacturing, requiring qualification for integration into memory flows.
  • Area Efficiency: The 2T cell, while eliminating the capacitor, adds routing complexity and increases active devices per bit.
  • Time to Market: Competition from existing and upcoming memory technologies (LPDDR6, HBM4) necessitates a timely production rollout.
• 0:08:42 Vertical Stacking Capabilities: A major advantage is its low-temperature deposition, allowing the memory structure to be built vertically after logic circuits are in place without disturbance.
• 0:09:17 Potential Applications for Stacking:
  • Embedded Memory: Stacking DRAM directly above processor cores to reduce latency and power, ideal for AI accelerators and High-Performance Compute (HPC).
  • High-Density Stacking: Building DRAM cells in vertical layers with control logic underneath, offering a simpler alternative to HBM and 3D NAND.
• 0:10:19 Addressing Reliability Concerns: IMC has tackled issues like Bias Temperature Instability (potential drift of IGZO cells under voltage/heat) by reducing indium content and operating in short bursts, meeting 5-year reliability targets. Hydrogen contamination was also addressed.
• 0:11:49 Future Outlook: The technology is aligned with EU manufacturing initiatives, but major memory vendors (Samsung, Micron, SK Hynix) have yet to publicly adopt it. AI accelerators are seen as the most likely early adopters due to their high memory bandwidth demands.