This video tutorial demonstrates the intricate process of creating a First Stage Bootloader (FSBL) for a Xilinx ZC102 development board, which features the Zynq UltraScale+ CPU, using the updated Vitis 2024 development environment. The presenter highlights specific "tricks" required by the new Vitis version to successfully generate the FSBL, including the crucial step of correctly configuring platform creation and separately generating the Zynq MP FSBL example design. The tutorial covers building the FSBL ELF file and then assembling a complete boot image (.BIN) by integrating the FSBL with PMU firmware, BL31, U-boot, and a device tree binary, ensuring correct exception levels and load addresses. The video concludes with a successful live demonstration of booting the ZC102 board using the newly created boot image, underscoring the FSBL's foundational role in initializing the system for higher-level bootloaders and operating systems.
Creating a First Stage Bootloader (FSBL) for Xilinx ZC102 with Vitis 2024
0:00 - Introduction to FSBL: The video's objective is to create a First Stage Bootloader (FSBL) for the Xilinx ZC102 board (featuring a Zynq UltraScale+ CPU) using Vitis 2024. FSBL runs on the CPU to load subsequent bootloaders like U-boot, which then loads the operating system. The presenter notes that Vitis 2024 makes this process "quite tricky."
0:50 - Creating the Vitis Platform Component: The first critical step is to create a new "Platform" component within Vitis. This platform defines the hardware and can be chosen from Xilinx's standard boards (like ZC102) or imported from a custom Vivado hardware export (.XSA file).
2:44 - Key Platform Configuration Detail: When creating the platform, it's essential to unselect the "Generate boot artifact" option. If selected here, it generates an FSBL that causes issues with the FSBL domain later.
3:57 - Generating the Zynq MP FSBL Application: A separate FSBL application is created by selecting "Zynq MP FSBL" from the "Example Design" window (specifically for UltraScale+ architectures; Zynq 7000 would use "Zynq FSBL"). During this step, the "FSBL domain" must be explicitly selected, and "Core number zero" manually chosen.
5:07 - Building the FSBL: The configured FSBL application is then built, which compiles the source code and generates the fsbl.elf file β the binary for the first stage bootloader.
5:27 - Creating the Boot Image (.BIN) File: The next step is to create a complete bootable image (boot.bin) using Vitis's "Create Boot Image" utility.
5:51 - Adding Boot Image Partitions: Various essential components are added as partitions to the boot image:
The generated fsbl.elf file (destination CPU: A53_0).
PMU firmware (pmu_firmware.elf).
BL31 (bl31.elf), with a mandatory exception level of EL3.
U-boot image (u-boot.elf), with a mandatory exception level of EL2.
Device Tree Binary, with a specified load address.
7:19 - Boot Image Generation and Verification: After adding all partitions, the boot.bin file is generated. The video concludes by demonstrating a successful boot of the ZC102 board using this boot.bin file, confirming that the FSBL and subsequent bootloaders are functional.
8:22 - When FSBL Modification is Needed: Generally, the FSBL doesn't require modification, but it might be necessary for custom hardware configurations involving unique clock settings or other special initializations during the initial boot phase.