This document details AMD's RDNA4 GPU architecture, presented at Hot Chips 2025, highlighting its strategic shift towards efficiency across gaming, raytracing, and machine learning workloads, rather than solely pursuing top-tier performance. Key architectural advancements include significant improvements in the media engine for faster, higher-quality, and lower-latency video encoding (H.264, H.265, AV1) and decoding, and a display engine that incorporates hardware-accelerated image sharpening and dramatically reduces multi-monitor idle power consumption through dynamic refresh rate management. The compute units benefit from scalar floating-point instructions and a new "split barrier" synchronization mechanism to enhance performance and efficiency. A substantially larger 8MB L2 cache and enhanced transparent compression across the SoC are introduced to optimize the memory subsystem, particularly benefiting raytracing by reducing off-chip data access. The RDNA4 design also integrates advanced Reliability, Availability, and Serviceability (RAS) features, robust security mechanisms, and leverages the Infinity Fabric for scalable and coherent memory access, all within a monolithic die chosen for its specific performance and cost targets. Overall, RDNA4 aims to deliver performance comparable to prior high-end generations but with a lower power budget and a more compact die size.
Summarizing AMD’s RDNA4 GPU Architecture at Hot Chips 2025
RDNA4 Architectural Focus: AMD's RDNA4 GPU architecture (RX 9000 line) prioritizes efficiency across rasterization, compute, raytracing, and machine learning, aiming for a significant leap in raytracing and ML performance.
Enhanced Media Engine:
High-end RDNA4 GPUs feature dual media engines with hardware acceleration for H.264, H.265, and AV1 video encoding and decoding.
Decoding speed is faster, enabling "race to idle" for power savings during video playback.
Targeted improvements for video encoding quality and lower latency are especially beneficial for streaming, with RDNA4 showing higher VMAF scores (e.g., preserving high-contrast text at lower bitrates).
Encoding speed has slightly improved from ~190 FPS (RDNA3.5) to ~200 FPS (RDNA4).
Innovative Display Engine:
Introduces a hardware-accelerated "Radeon Image Sharpening" filter implemented directly in the display engine, ensuring no performance impact and improved power efficiency compared to shader-based solutions.
Significantly reduces multi-monitor idle power consumption by dynamically lowering memory clocks using variable refresh rates on FreeSync displays.
Features an intermediate GDDR6 power state, allowing for more granular power management in complex multi-monitor setups.
Compute Unit Advancements:
The Workgroup Processor (WGP) includes major improvements for raytracing, such as enhanced units and wider BVH nodes, along with dynamic register allocation and a scheduler optimized to prevent false memory dependencies.
The scalar unit now supports floating-point instructions (a feature debuted in RDNA3.5), expanding opportunities for power-saving scalar offloads and offering lower latency for some FP32 operations (4 cycles for scalar vs. 5 for vector).
A new "split barrier" mechanism (s_barrier_signal and s_barrier_wait) allows threads to signal completion and perform independent work before waiting for others, reducing performance stalls.
Optimized Memory Subsystem:
The largest RDNA4 variants feature a substantial 8 MB L2 cache (increased from 6 MB in RDNA3), significantly benefiting raytracing workloads by reducing the need to access the slower Infinity Cache.
The L1 cache is notably absent, potentially due to reallocating transistor budget to the larger L2 or prior generations' low L1 hit rates.
Improved transparent compression is integrated throughout the SoC (including display and media engines), which helps reduce bandwidth requirements and enhance power efficiency.
SoC and Infinity Fabric Integration:
Incorporates Reliability, Availability, and Serviceability (RAS) features, including parity and ECC for error detection and correction, with driver-based re-initialization for unrecoverable errors.
Includes enhanced security measures like private buses and protected register access, with terminology hinting at shared SoC design efforts with AMD's CPU division.
The Infinity Fabric memory-side subsystem features 16 Coherent Station (CS) blocks, each with 4 MB of cache (total 64MB Infinity Cache), providing coherent memory access and supporting dynamic voltage and frequency scaling (DVFS) for power savings.
Retains flexible configurability (die harvesting) to create different GPU SKUs by selectively disabling components.
AMD opted for a monolithic die design for RDNA4, balancing performance goals, package assembly, and cost for its target size.
Overall Strategy and Performance Summary:
RDNA4 represents a strategic shift towards improving efficiency rather than solely achieving top-end performance.
The RX 9070 offers comparable rasterization performance to the RX 7900XT but with a lower power budget, less memory bandwidth, and a smaller last-level cache.
It demonstrates leadership in raytracing workloads, aligning with AMD's architectural goals.
Achieves its efficiency through innovations like enhanced compression, improved raytracing structures, and a larger L2 cache, all within a compact 356.5 mm² die and a 256-bit GDDR6 memory setup.