Pavl introduces his ongoing open-source hardware initiatives in software-defined radio (SDR), aiming to provide more affordable and advanced alternatives to commercial options like Red Paya boards, which he notes have become expensive and technologically aging. He details his first successful project: an Analog-to-Digital Converter (ADC) expansion board designed for existing QMtech mainboards. This solution offers 16 multi-channel receivers with performance comparable to the Red Paya SDR Lab but at a significantly lower cost (around €200 for the complete system), leveraging accessible low-volume custom PCB assembly services like JLCPCB. Furthermore, Pavl outlines his ambitious next project: a completely open-source hardware platform comprising a Kintex 7 FPGA mainboard and a modular expansion board featuring dual 250 MHz ADCs and a 10 Gigabit Ethernet (SFP+) interface for high-bandwidth data transfer and electrical isolation. The presentation emphasizes a community-driven design approach, focusing on cost-effectiveness, modularity, and pushing the boundaries of performance in amateur radio SDR applications.
Summary:
0:08 Introduction to Pavl's SDR Projects: Pavl, known for his Red Paya FPGA images, introduces his new open-source SDR hardware projects, aiming for more affordable and advanced solutions in amateur radio.
2:01 Red Paya Boards & Application Context: Pavl's popular SDR applications for Red Paya boards provide up to 16 multi-channel receivers, but he notes the Red Paya hardware is becoming expensive and outdated compared to current industry advancements.
5:10 Motivation for Custom Hardware: Progress in FPGA/System-on-Chip (SoC) families and highly accessible custom PCB assembly services (like JLCPCB) now make developing cost-effective, high-performance SDR hardware feasible for low volumes.
6:10 Cost Discrepancy & Opportunity: A QMtech board with the same SoC as the €780 Red Paya SDR Lab can be significantly cheaper (e.g., €79) without ADCs/DACs, presenting a clear opportunity for custom solutions.
8:18 Project Requirements & Goals (First Project): Based on community feedback, Pavl's first hardware project focused on creating a low-price, receiver-only system with 16 channels compatible with popular SDR software (e.g., HDSDR, OpenWebRX).
9:21 First Project Development Plan: The plan involved using a QMtech mainboard (with FPGA and Gigabit Ethernet) and developing a custom expansion board with a fast ADC, clock generator, power supplies, input protection, and a low-pass filter.
11:30 ADC Expansion Board Design & Cost: Designed with KiCad, the first expansion board features a fast ADC with LVDS outputs, a crystal oscillator, voltage regulators, and a 30 MHz low-pass filter. Ordering two assembled boards cost approximately €180, making each expansion board about €90.
13:01 Cost-Effective SDR System: The combined system (QMtech board + expansion board) achieves a total cost of around €180, significantly undercutting the price of the Red Paya SDR Lab while offering comparable performance.
14:13 First Project Success: The project is deemed successful, with source code and documentation publicly available, and several dozen expansion boards having been successfully ordered by radio operators in various countries.
14:56 Next Project: Fully Open-Source & High-Performance: Pavl's next endeavor is to develop both the main board and a new expansion board entirely as open-source hardware.
15:06 Next Project Main Board Details: The new main board will feature a Kintex 7 FPGA, an SFP+ connector for 10 Gigabit Ethernet, and a SODIMM connector for the expansion board, with an estimated cost of €180 per board in low volumes.
15:39 Next Project Expansion Board Details: The upcoming expansion board will include a faster, dual-input ADC with a 250 MHz sampling rate, currently in the design phase.
17:06 Conclusion & Invitation: Pavl highlights the amazing capabilities of JLCPCB for custom hardware production and invites interested individuals to join the discussion for the new 10 Gigabit Ethernet project on the Next Gen SDR mailing list.
19:47 10 Gigabit Software Approach: For the 10 Gigabit system, Pavl plans to send raw samples as UDP packets from the FPGA to the computer without downsampling, leveraging existing software capable of processing 100+ mega samples per second, though on-FPGA downconverters are also possible.
23:15 RF Front End Strategy (Next Project): The initial focus for the expansion board is a dual-channel 250 Msps bassband ADC, based on community interest in synchronized RF inputs and electrical isolation via SFP+. The modular design allows for future development of boards with high-frequency mixers or integrated radio chips.
26:51 Timestamping Plans: Relative timestamping (packet numbering) for samples is planned, with potential for absolute timestamping via GPS synchronization in future iterations.
28:07 Cost Scaling with Volume: Assembly costs tend to decrease with higher volumes (e.g., from two to five boards), making components and taxes the primary cost drivers for small-batch custom PCBs.
30:00 Transmitter Board Possibility: Pavl acknowledges the feasibility of designing a modular transmitter board, possibly integrating radio components similar to those on SDR Pluto, to provide transceiver capabilities and access to higher frequencies via the SFP+ interface.
31:27 High-Speed Design Challenges: The high-speed design for the 250 MHz ADC and 10 Gigabit Ethernet (requiring careful differential line length matching) on the new project's boards is challenging but something Pavl is confident in tackling based on prior experience.
33:55 Analog Performance of First Board: Pavl confirms that the analog performance of his first ADC expansion board for the QMtech system is comparable to the Red Paya SDR Lab, a conclusion supported by his own and other users' reception tests.