This article from Chips and Cheese provides a deep dive into the memory subsystem of Intel's new Xeon 6 server platform, using a 96-core Xeon 6 6985P-C processor tested via an AWS cloud instance. The analysis focuses on Intel's scalable chiplet strategy, which separates compute dies (containing cores and DRAM controllers) from IO dies, connecting them with a high-speed mesh interconnect via EMIB technology. The test system was configured in Sub-NUMA Clustering (SNC3) mode, partitioning the chip into three nodes to improve local access latency. Performance benchmarks reveal that while Xeon 6 achieves a massive increase in total DRAM bandwidth (over 690 GB/s) and maintains excellent core-to-core coherency latency, it suffers from higher L3 and DRAM latency compared to its predecessor (Emerald Rapids) and AMD's competitor (Turin/Zen 5). The article contrasts Intel's "logically monolithic" design philosophy against AMD's more segmented approach, concluding that while Intel's engineering is impressive, its design faces significant trade-offs between unified cache access and memory latency.
An In-Depth Analysis of Intel's Xeon 6 Memory Architecture
Scalable Chiplet Design: Intel's Xeon 6 adopts a new chiplet strategy to compete with high-core-count rivals. It separates core and DRAM controllers onto advanced "compute dies" while moving lower-speed functions to separate "IO dies." The tested 96-core model (6985P-C) uses three compute dies and two IO dies.
Sub-NUMA Clustering (SNC3): By default, the chip operates in SNC3 mode, dividing itself into three separate NUMA nodes. This partitions the L3 cache and memory, ensuring cores have low-latency access to the resources on their own compute die.
L3 Cache Performance: The L3 cache offers a huge 160 MB pool per die but has a latency of over 33 ns, which is a slight regression compared to the previous Emerald Rapids generation and significantly slower than AMD's Zen 5.
DRAM Latency Trade-offs: Despite using fast DDR5-7200 memory and placing memory controllers directly on the compute dies, the Xeon 6 exhibits higher DRAM latency than both its predecessor and AMD's Turin platform. Accessing memory on an adjacent die adds an additional ~26 ns of latency.
Massive Bandwidth Improvement: The platform's key strength is bandwidth. With 12 memory controllers, it achieves a total DRAM bandwidth of 691.62 GB/s, more than double the ~323 GB/s of Emerald Rapids. Cross-die bandwidth over the mesh interconnect is also exceptionally high.
Design Philosophy: Intel vs. AMD: The analysis highlights a fundamental difference in strategy. Intel aims for a "logically monolithic" chip with a single, high-speed mesh interconnect spanning all dies, which provides excellent core-to-core latency (50-80 ns). In contrast, AMD uses a multi-level interconnect (Infinity Fabric) that is less complex but creates clearer boundaries between core clusters.
Key Takeaway: Intel's Xeon 6 design makes a direct trade-off. It achieves a more unified cache system and superior core-to-core communication at the cost of higher L3 and DRAM latency. The article questions whether the benefits of this complex monolithic approach are worth the performance compromises, especially as core counts continue to scale.