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Abstract:
This article provides a deep-dive technical analysis of the AMD EPYC 9355P, a 32-core Zen 5 server processor. The analysis focuses on how AMD leverages a lower core count design to maximize per-core performance through high clock speeds, a high L3 cache-to-core ratio (using eight 4-core CCDs), and a high-bandwidth "GMI-Wide" interconnect. The investigation thoroughly examines the memory subsystem, comparing various NUMA configurations (NPS1, NPS2, NPS4) and finding surprisingly low penalties for cross-node access, resulting in near-monolithic performance characteristics. The article also quantifies the significant bandwidth and latency-under-load advantages of the GMI-Wide interface over standard desktop implementations. Benchmark comparisons against desktop CPUs and competing server chips from Intel highlight the 9355P's strengths in memory-bandwidth-intensive workloads. The conclusion is that the EPYC 9355P is a well-balanced chip and that AMD's hub-and-spoke IO die architecture continues to be a highly effective and competitive design.
A Deep Dive into the AMD EPYC 9355P Zen 5 Server CPU
Introduction: A Focus on Per-Core Performance: The AMD EPYC 9355P is a 32-core Zen 5 server processor uniquely designed for high per-core performance. It achieves this by distributing its 32 cores across eight separate CPU dies (CCDs), enabling each group of four cores to access a full 32 MB L3 cache and connect to the central IO die via a high-bandwidth "GMI-Wide" interface.
Memory Subsystem & NUMA: Near-Monolithic Performance: The chip offers multiple NUMA configurations (NPS1, NPS2, NPS4) to partition cores and memory. However, testing reveals very low latency penalties for cross-node memory access, making the chip feel more monolithic than competing designs from Intel. The default NPS1 mode, which stripes memory across all 12 controllers, is found to be highly effective for most workloads.
Looking into GMI-Wide: Eliminating Bottlenecks: This key feature doubles the connection bandwidth between each CCD and the IO die (64B/cycle). A single CCD can achieve nearly 100 GB/s of read bandwidth, a substantial increase over desktop parts. Crucially, it improves latency control under heavy load, preventing the performance corner cases and latency spikes seen in consumer chips.
SPEC CPU2017: Bandwidth is King: While slightly behind top-tier desktop chips in pure single-thread speed due to lower clocks, the EPYC 9355P excels in bandwidth-intensive multi-core workloads. In SPECfp_rate tests, its robust memory subsystem and GMI-Wide interconnect allow it to outperform both its desktop counterparts and competing Intel Xeon CPUs in scenarios where memory bandwidth is the limiting factor.
Final Words: A Winning Architectural Formula: The EPYC 9355P demonstrates the strength and maturity of AMD's server architecture. Its "hub-and-spoke" design with a central IO die provides excellent, consistent memory performance that feels monolithic, offering a distinct and currently superior approach to DRAM access compared to competitors who place memory controllers on the compute dies.