AMD's Turin: 5th Gen EPYC Launched - A Deep Dive into Memory and Performance

• Memory Bandwidth:
  • Single Thread: The EPYC 9575F achieves ~52 GB/s read, ~48 GB/s write, and ~95 GB/s read-modify-write bandwidth.
  • Single CCD: A single core can utilize nearly half the total CCD read bandwidth, ~55% of write bandwidth, and over two-thirds of read-modify-write bandwidth.
  • Full Socket: The 9575F reaches nearly 99% of the theoretical 576 GB/s read bandwidth, with writes and adds at 435 GB/s and 453 GB/s respectively.
  • Socket to Socket: Performance on the Volcano platform with 3 GMI links is similar to Bergamo, highlighting the impact of interconnect.
• Memory Latency:
  • Unloaded: Turin's unloaded latency is comparable to Genoa.
  • Loaded (Single CCD): A loaded CCD shows a ~39 ns increase compared to unloaded latency.
  • Loaded (Full System): A fully loaded system shows a ~31 ns increase.
  • Core to Core: Intra-CCD latency is ~45 ns, inter-CCD latency is ~150 ns, and socket to socket latency is ~260 ns, representing an increase from Genoa.
• Clock Speed:
  • Single-Threaded: All 64 cores can reach 5 GHz.
  • Memory Bandwidth Test: All 8 cores on a CCD achieved 5 GHz during testing.
  • Cinebench: All-core frequency hovered around 4.3 GHz.
  • Web Server Workload: All-core frequency reached ~4.9 GHz in less vectorized workloads.
• Key Takeaways:
  • Turin represents a significant generational update, particularly for memory bandwidth and frequency.
  • High core count SKUs (9755, 9965) cater to hyperscalers, while lower core count, high-frequency SKUs (9575F) target the enterprise market.
  • The 9175F with 16 cores and 512MB L3 cache is designed for specific workloads, likely those with high per-core licensing costs or needing a large cache.
  • While not as revolutionary as Naples to Rome, Turin builds upon the improvements seen in Milan to Genoa.
  • The competitive server CPU landscape offers a wealth of options compared to the Intel-dominated market of the past.