AMD's Turin: 5th Gen EPYC Launched - Key Takeaways
Increased Memory Bandwidth: Turin boasts 12 DDR5-6400 memory channels, achieving near-theoretical 576 GB/s read bandwidth, significantly higher than desktop Zen 5 due to dual GMI links and a 32B write link per GMI. (Supports 6000 MT/s with 1 DIMM, 4400 MT/s with 2 DIMMs per channel)
Enhanced Socket to Socket Bandwidth: Similar to Bergamo, Turin achieves impressive socket to socket bandwidth with 3 GMI links.
Comparable Memory Latency: Unloaded latency is similar to Genoa, while loaded latency shows a ~39ns increase with a single CCD loaded and ~31ns with the full system loaded, indicating consistent behavior regardless of load.
Higher Core to Core Latency: Compared to Genoa, Turin experiences a latency increase, especially within a CCD (Intra-CCD: ~45ns, Inter-CCD: ~150ns, Socket to Socket: ~260ns).
Impressive Clock Speed: The 9575F can hit 5GHz on all 64 cores in single-threaded tests and sustains around 4.3GHz in Cinebench with all threads active. Some workloads see up to 4.9GHz all-core performance.
Varied SKU Offerings: Turin caters to both hyperscalers (high core count 9755, 9965) and the traditional enterprise market (lower core count, high-frequency 9575F).
Evolutionary Update: While not a revolutionary jump like Naples to Rome, Turin represents a significant evolution similar to Milan to Genoa, with increased bandwidth, core count, and updated cores.
Competitive Ecosystem: Turin offers strong value in a competitive server market, appealing to a wide range of users with its performance and feature set.
Specific Workloads: The 9175F with 16 cores and 512MB L3 cache is designed for workloads sensitive to per-core licensing costs or those requiring large amounts of cache.
Note: This summary focuses on the key technical aspects of Turin. The transcript also includes discussion about pricing, availability, and comparisons with other CPUs, which are not included in this specific summary.