This blog post presents a comprehensive walkthrough of the design, construction, and testing of a homemade 6 GHz pulse compression radar. The author details the project from concept to a functional prototype, contrasting pulse radar with simpler FMCW designs and addressing the significant challenges involved, such as the need for high-speed data conversion and precise timing. The radar is built on a Software-Defined Radio (SDR) architecture, featuring a Zynq 7020 FPGA, a 250 MSps ADC, and a 500 MSps DAC. Key design aspects covered include the zero-IF RF architecture, meticulous 6-layer PCB design with considerations for DDR3 memory routing and extensive power supply filtering, and the digital calibration required to compensate for hardware non-idealities like LO leakage and DC offset. The system's software pipeline performs pulse compression, Range-Doppler processing, Constant False Alarm Rate (CFAR) target detection, and Kalman filter tracking. Real-world tests successfully demonstrate the radar tracking vehicles at distances up to 400 meters, with a detailed analysis of performance in both single and dual antenna configurations. The author concludes by sharing the final project cost of approximately $570 for two boards and making the schematics publicly available.
Building and Testing a 6 GHz Pulse Compression Radar
Introduction - Pulse vs. FMCW Radar: Pulse radars are more complex and expensive than FMCW radars but are better suited for long-range applications. Key challenges include the need for very fast transmit/receive switching to avoid a large minimum detection distance and high-speed ADCs (hundreds of MHz) to capture the RF bandwidth, which determines range resolution.
System Architecture - Pulse Compression: The radar generates an arbitrary waveform (e.g., a linear frequency sweep) and finds targets by calculating the convolution between the transmitted and received signals. This processing is done efficiently using FFTs. By sending a burst of pulses, a Range-Doppler map is created, allowing for the measurement of both a target's distance and its velocity based on phase changes between pulses.
Hardware Selection - Core Components: The design is built around key high-speed components selected for a minimal budget.
ADC: Texas Instruments ADS4229 (250 MHz, 12-bit, dual-channel) was chosen as the best value for its sample rate.
FPGA: A Xilinx Zynq 7020 was sourced from China for $17 (versus $173 from official resellers) to handle the high-speed data processing and timing.
RF Design - 6 GHz Operation: The RF front-end operates around 6 GHz and uses a zero-IF (direct conversion) architecture to minimize cost.
Power Amplifier: A Skyworks SE5004L provides approximately 2W of peak output power.
T/R Switch: A MASW-007588 switch with a 55 ns switching time is used for single-antenna operation. This switching time corresponds to a minimum dead zone of 16.5 meters.
Calculated Range: The theoretical maximum detection range is calculated to be 1200 meters for a 1mΒ² target.
PCB Design - High-Speed and RF Challenges: A 6-layer PCB was designed to manage the complex routing.
DDR3 Memory: Careful length-matching and impedance control (using 60-ohm traces and 50-ohm termination) were required for the high-speed DDR3 memory interface.
Power Supply Filtering: To prevent switching noise from interfering with sensitive analog signals, a multi-stage filtering approach with LDOs and ferrite beads was implemented to achieve over 100 dB of noise attenuation.
Calibration - Correcting Hardware Imperfections: The zero-IF architecture requires digital calibration to achieve good performance.
The system compensates for ADC DC offset and transmitter LO leakage.
A key finding was that using a frequency sweep offset from DC (a low-IF pulse) completely removed artifacts caused by AC coupling capacitors, resulting in a much cleaner impulse response with sidelobes only 2 dB higher than the theoretical ideal.
Signal Processing - From Samples to Targets: A software pipeline processes the raw ADC data to identify and track targets.
A Range-Doppler map is generated to visualize targets by distance and velocity.
A Constant False Alarm Rate (CFAR) algorithm is used to detect targets by estimating the local noise floor.
A Kalman filter is implemented to track detected objects over time, associating new detections with existing tracks.
Field Testing - Real-World Results: The radar was tested by monitoring road traffic.
Dual Antenna Test: Using separate transmit and receive horn antennas, the radar successfully detected and tracked cars up to 400 meters away, a limit imposed by the line of sight.
Single Antenna Test: When using a single antenna with the T/R switch, the system could still detect targets, but with a minimum practical range of about 40 meters due to the pulse length and switching time.
Conclusion - Cost and Availability: The total cost for manufacturing and assembling two boards was approximately $570. The project demonstrates a successful implementation of a modern pulse compression radar on a hobbyist budget, and the full schematics are available for reference.