Intel revealed their upcoming client System-on-Chip (SoC), Panther Lake (PTL), at ITT 2025, showcasing an evolutionary design leveraging multiple fabrication nodes across three primary tiles: Compute (Intel 18A), GPU (Intel 3 or TSMC N3E), and Platform Controller (TSMC N6). PTL features the new Xe3 GPU architecture, which sees improvements like render slices supporting up to six Xe Cores and Variable Register Allocation, translating to a claimed 50% performance uplift over Lunar Lake’s iGPU. The new P-Cores (Cougar Cove) and E-Cores (Darkmont) offer generational improvements in cache and branch prediction, yielding a claimed 10% single-threaded improvement over prior architectures. PTL also introduces upgrades to the NPU (FP8 support, 40% size reduction) and Media Engine (AVC 10b support). The official launch is slated for CES 2026.
Panther Lake’s Reveal at ITT 2025: Key Details and Takeaways
SoC Layout and Tiling Strategy (Starting: SoC Layout): Panther Lake utilizes three active tiles: the Compute Tile (P-Cores, E-Cores, NPU, 8MB Memory Side Cache), the dedicated GPU Tile, and the Platform Controller Tile (I/O IP).
Fabrication Nodes: The Compute Tile is built on Intel’s new 18A process. The GPU Tile uses either Intel 3 (smallest config) or TSMC N3E (largest config). The Platform Controller Tile likely reuses the same die fabricated on TSMC N6.
Configurations and I/O Variation (Starting: Smallest Configuration): PTL offers configurations ranging from 4 P-Cores/4 LP E-Cores up to 4 P-Cores/8 E-Cores/4 LP E-Cores.
Middle Config: Adds 8 E-Cores sharing an 18MB L3 cache and expands I/O to include 20 total PCIe lanes (12 Gen 5, 8 Gen 4).
Largest Config: Features the largest iGPU Intel has made for a client SoC—a 12 Xe3 core GPU—at the expense of dropping the I/O back down to 12 PCIe lanes.
Xe3 GPU Architecture (Starting: Xe3 Architecture): This generation is confusingly marketed under the older Intel Arc B-Series branding (not C-Series).
Structural Improvements: The Xe3 render slice can now accommodate up to 6 Xe Cores (up from 4).
Cache: The 12 Xe core configuration includes a 16MB L2 cache, reducing SoC fabric traffic by up to 36%.
Front-End and Register Allocation: Compute throughput remains the same, but the L1/SLM capacity increases to 256KB. Xe3 introduces "Variable Register Allocation," allowing threads to allocate registers in 32-register increments up to 256, improving register file utilization.
Performance Takeaway: Intel claims an approximate 50% performance uplift for the 12 Xe3 core iGPU compared to Lunar Lake’s iGPU, particularly in 3D Mark and popular games.
Cougar Cove (P-Core) and Darkmont (E-Core) (Starting: Cougar Cove and Darkmont): CPU cores are characterized as evolutionary rather than revolutionary.
Cougar Cove (P-Core): Features a 50% increase in TLB capacity and improved Branch Predictor Unit (BPU) algorithms ported from Lunar Lake testing.
Darkmont (E-Core): Sees major BPU improvements, increased structure sizes, and improved prefetcher.
Shared Gain: Both cores feature improved memory disambiguation (Store to Load) behavior using unique implementations.
CPU Performance Claims: Intel claims a 10% single-threaded improvement over Arrow Lake/Lunar Lake and a 40% performance per watt improvement over Arrow Lake.
NPU and Media Engine Upgrades (Starting: NPU and Media Engine): The Media Engine now supports AVC 10b decode and encode, while the NPU gains FP8 support and is shrunk by about 40%.
Launch Schedule (Starting: Final Words): The official launch and SKU details for Panther Lake are scheduled for CES 2026, with units expected on shelves shortly after.
Future Arc Plans (Sidenote): Intel also announced an inference-focused GPU based on the Xe3P microarchitecture, featuring up to 160GB of LPDDR5X, sampling in H2 2026.