Abstract:

This video introduces Helion, a new high-level Domain-Specific Language (DSL) designed for authoring high-performance Machine Learning kernels. Positioned between the high-level abstractions of PyTorch and the low-level control of DSLs like Triton, Helion aims to simplify kernel development by allowing developers to write in a "PyTorch with tiles" style. The core feature of Helion is its sophisticated, integrated autotuner, which systematically explores thousands of underlying Triton kernel implementations (varying tile sizes, indexing modes, reduction strategies, and more) generated from a single, high-level Helion kernel. This approach automates the tedious process of manual optimization, saving developer time and enabling excellent performance portability across different hardware generations and vendors, including NVIDIA's B200 and AMD GPUs. The compiler reuses Torch Inductor's backend to support standard PyTorch operations directly within kernels, further simplifying the authoring experience. The presentation includes practical examples, debugging techniques, performance benchmarks showing Helion outperforming handwritten Triton, and a walkthrough of writing a complex attention kernel.

Helion: A Guide to the High-Level Kernel DSL

• 0:50 - Core Philosophy: Helion is introduced as a high-level DSL for ML kernels that sits between PyTorch and Triton. Its goal is to provide more control than PyTorch Compile without requiring developers to manage low-level details.
• 1:55 - The Autotuner Advantage: Helion's key differentiator is its integrated autotuner. It automatically searches a vast configuration space (thousands of variations) from a single Helion kernel to find the most performant implementation, saving significant human effort and improving hardware portability.
• 3:22 - Kernel Structure: A Helion kernel consists of two parts: a "host side" with standard PyTorch code for setup, and a "device side" defined by hl.tile loops. This device-side code is guaranteed to be compiled into a single, fused Triton kernel.
• 5:18 - High-Level Primitives: The primary construct is hl.tile, which defines the iteration space. The autotuner automatically handles critical details like tile sizes, iteration order, loop flattening, and swizzling.
• 6:08 - Autotuning Search Space: The autotuner explores various optimization strategies, including different indexing modes (e.g., block pointers, tensor descriptors), reduction loop implementations, launch grid configurations (1D, 2D, persistent), and loop reordering.
• 17:03 - PyTorch Integration: Helion reuses the Torch Inductor compiler backend, allowing developers to use standard torch operations (e.g., torch.softmax, torch.mean) directly inside the kernel's device code.
• 22:33 - Impressive Performance: Benchmarks demonstrate that Helion's autotuned kernels are highly competitive, often outperforming handwritten Triton code and other compilers on modern hardware like NVIDIA's H100/B200 and AMD GPUs.
• 29:11 - Getting Started & Debugging: The language is available via pip install helion. The talk highlights useful environment variables for development, such as HELION_PRINT_OUTPUT_CODE=1 to inspect the generated Triton code and HELION_AUTOTUNE_EFFORT=none to bypass the lengthy tuning process for quick correctness checks.
• 37:04 - Advanced Manual Control: While the autotuner handles most optimizations, Helion provides escape hatches for expert users to manually control aspects like shared block sizes for reductions (hl.register_block_size) and cache behavior (eviction_policy).
• 50:14 - Kernel Authoring Strategy: The key mental model for writing a Helion kernel is to identify which dimensions can be parallelized (placed in the outer hl.tile loop, which maps to the GPU launch grid) and which must be executed sequentially (placed in inner hl.tile loops, for reductions).