This video introduces Helion, a new high-level Domain-Specific Language (DSL) for authoring high-performance machine learning kernels. Presented by its creators from the PyTorch compiler team—Jason Ansel, Oguz Ulgen, and Will Feng—Helion is designed to sit between the high-level abstraction of PyTorch and lower-level DSLs like Triton. Its core philosophy is to simplify kernel development by allowing authors to use familiar PyTorch syntax and concepts ("PyTorch with tiles") while abstracting away complex, low-level details such as memory indexing, block size management, and boundary condition masking.
The key differentiator for Helion is its powerful, integrated autotuner, which explores a vast search space of thousands of potential Triton kernel configurations from a single, high-level Helion implementation. This approach not only achieves performance that often surpasses handwritten, specialized kernels but also ensures portability across different hardware generations and vendors. The presentation includes performance benchmarks on NVIDIA H100/B200 and AMD GPUs, a deep dive into the compiler's architecture which reuses the Torch Inductor backend, and hands-on demonstrations of writing kernels for element-wise operations, matrix multiplication, and a complete fused attention implementation.
Helion: A High-Level DSL for Simplified and Performant ML Kernels
0:50 Motivation and Philosophy: Helion is a new DSL designed to give developers more control over kernel generation than Torch Compile, without requiring the low-level expertise needed for languages like Triton. It aims to be closer to PyTorch concepts, making kernel authoring more accessible.
1:55 The Core Differentiator: A Powerful Autotuner: Helion's main feature is a sophisticated autotuner that generates and tests thousands of Triton kernel variations from a single Helion kernel.
Key Takeaway: This saves significant human effort in performance tuning and provides excellent hardware portability, as kernels can be re-tuned for new hardware instead of being rewritten.
3:17 The Programming Model: "PyTorch with Tiles": A Helion kernel is defined by an hl.kernel decorator. The core logic resides within hl.tile loops, which operate on "tiles" (sub-blocks) of tensors. Crucially, standard PyTorch operations (torch.addmm, torch.softmax, etc.) can be used directly on these tiles inside the kernel.
6:28 Abstracting Low-Level Details: The autotuner automatically handles and optimizes many tedious aspects of kernel writing:
Indexing & Block Sizes: A single PyTorch-style indexing is automatically lowered to the most performant Triton indexing mode (e.g., pointer math, block pointers).
Reductions: Automatically converts simple reductions into efficient, tiled reduction loops to avoid register pressure.
Masking: Automatically manages boundary conditions, which is often error-prone to do manually.
On an H100 GPU, Helion shows strong performance across various input sizes for RMS Norm, outperforming other specialized solutions in different regimes.
On B200, Helion achieves a geomean speedup of 3.2x over eager PyTorch and is nearly 2x faster than a repository of expert-handwritten Triton kernels, thanks to the autotuner's extensive search.
Similar strong performance is demonstrated on AMD hardware, highlighting its portability.
25:07 Compiler Architecture: Helion is a Python-embedded DSL that reuses the Torch Inductor compiler as its backend. This allows it to seamlessly support a vast library of PyTorch operations inside its kernels without needing custom implementations.
40:37 Debugging and User Experience: Helion provides several environment variables for an easier development workflow:
HELION_PRINT_OUTPUT_CODE=1: Prints the final generated Triton code.
HELION_AUTOTUNE_EFFORT=none: Disables autotuning for quick correctness checks.
HELION_INTERPRET=1: Executes the kernel logic using PyTorch's eager mode for easier debugging, bypassing Triton entirely.
51:54 How to Write a Helion Kernel (Attention Example): The primary mental model for writing a Helion kernel is to decide which dimensions can be parallelized and which must be executed sequentially.
Parallel dimensions are placed in the outer hl.tile loop, which defines the kernel's launch grid.
Sequential/Reduction dimensions are placed in inner hl.tile loops.
1:01:19 Composability and Future Work: Helion kernels compile down to standard CUDA kernels, making them fully composable with PyTorch, Torch Compile, and existing Triton kernels. Future plans include exploring "mega-kernels" capable of fusing larger parts of a model into a single kernel launch.