This video presents a detailed analysis of the silicon die floor plan for a PIC12F683 microcontroller, based on high-resolution imagery captured in a previous part. The video begins with a comprehensive safety briefing on the hazards and mitigation techniques for handling nitric acid and solvents during chip decapsulation, emphasizing engineering controls, small-scale reactions, thermal mass management, and waste neutralization.
The core of the video is a systematic identification of the microcontroller's functional blocks. Key areas identified include the main program flash (showing a 14-bit structure), a smaller data EEPROM, and the data SRAM, which is recognized by its classic "donut and I-beam" 6T cell layout typical for a 350nm process. The CPU core is deconstructed into its instruction decoding logic, 8-bit ALU/data path, and a PLA-like structure for microcode sequencing. An interesting discovery is made in the configuration registers, where a 13-bit physical fuse structure is found for the 12-bit calibration word, suggesting an undocumented configuration bit. Analog components, including the 10-bit ADC, comparators, and oscillators, are located. The analysis concludes by identifying the high-voltage tolerant circuitry on the GP3/MCLR pin used for programming mode entry and provides key die metrics, including a size of 4.212 mm² and an estimated gate count of 14,100.
Decoding the PIC12F683: A Tour of its Silicon Die
0:00:43 Chemical Safety Procedures: The video starts with a critical safety discussion on the chip decapsulation process. It details the risks of mixing nitric acid and solvents and outlines several mitigation strategies: working in a fume hood, using micro-liter scale quantities, employing fire-retardant PPE, separating waste streams, and using the high thermal mass of bulk solvent to prevent exothermic reactions from reaching ignition temperatures.
0:06:16 Device Floor Plan Overview: The analysis begins with a top-metal layer overview, moving to a de-layered image that clearly reveals the underlying silicon structures and functional blocks of the microcontroller.
0:07:09 Program Flash Memory: The main memory array is identified as the program flash. Its structure is consistent with the processor's 14-bit instruction word, visually divided into sections corresponding to the data and instruction buses.
0:08:06 SRAM Identification: A smaller memory array is identified as the SRAM (data memory) due to its distinct "donut and I-beam" cell layout, a classic design for 6-transistor SRAM cells on older process nodes like this 350nm chip.
0:09:04 Data EEPROM & Analog Blocks: A very small array using flash-style cells is identified as the data EEPROM. Nearby analog blocks containing large capacitors and polysilicon resistors are deduced to be the internal RC oscillator and crystal driver circuits.
0:09:54 CPU Core Breakdown: A large, regular block of digital logic is identified as the CPU core. Symmetries in the layout help distinguish its components: a section with 13-way symmetry is linked to instruction decoding, an 8-way symmetrical section is identified as the 8-bit accumulator and ALU, and a PLA-like structure is believed to be the microcode ROM for instruction sequencing.
0:11:10 The Mystery of the Configuration Fuses: The video highlights two columns of large non-volatile memory cells that function as configuration "fuses." While the configuration word has 12 bits, the calibration word's physical layout has 13 bits. It's hypothesized that the extra bit is an undocumented feature mapped to a reserved bit in the calibration register.
0:14:19 Analog Peripherals (ADC & Comparator): Additional analog circuits are located, including the 10-bit Analog-to-Digital Converter (ADC), which is identified by a structure with 10-way symmetry.
0:16:22 High-Voltage Programming Pin: The I/O buffer for the GP3/MCLR pin is shown to have significantly larger transistors than other pins. This is to handle the 12-volt signal required to force the chip into its high-voltage programming mode.
0:17:57 Die Statistics and Metrics: The analysis concludes with key physical measurements. The die size is 1.945 mm x 2.166 mm. Based on cell and metal pitch dimensions, the logic library is estimated to have a density of around 10,580 gates/mm², leading to a total estimated logic gate count of approximately 14,100 for the entire device.